Latency is detrimental to interactive systems, especially pseudo-physical systems that emulate real-world behaviour. It prevents users from making quick corrections to their movement, and causes their experience to deviate from their expectations. Latency is a result of the processing and transport delays inherent in current computer systems. As such, while a number of studies have hypothesized that any latency will have a degrading effect, few have been able to test this for latencies less than ∼ 50 ms. In this study we investigate the effects of latency on pointing and steering tasks. We design an apparatus with a latency lower than typical interactive systems, using it to perform interaction tasks based on Fitts's law and the Steering law. We find evidence that latency begins to affect performance at ∼ 16 ms, and that the effect is non-linear. Further, we find latency does not affect the various components of an aiming motion equally. We propose a three stage characterisation of pointing movements with each stage affected independently by latency. We suggest that understanding how users execute movement is essential for studying latency at low levels, as high level metrics such as total movement time may be misleading.

Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGap (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs, utilizing hardware multiplexed data paths. One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap impose few limits on the architecture and thus design freedom. NoGap does not assume a fixed processor template and is not a data flow synthesizer. To reach this flexibility NoGap makes heavy use of the compositional design principle. This paper describe NoGapCL, a flexible common language for processor hardware description. A RISC processor using NoGapCLhas been constructed with NoGap in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178 MHz in a Virtex-4 LX80 speedgrade 12.

Flexible Application Specific Instruction-set Processors (ASIPs) are starting to replace monolithic Application Specific Integrated Circuits (ASICs) in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. Novel Generator of Accelerators And Processors (NoGap) is a tool for ASIP design utilizing hardware multiplexed data paths. One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap imposes few limits on the architecture and thus design freedom. To prove that NoGap can be used to design complex data paths a reimplementation of a floating point adder/subtracter previously implemented using Verilog with FPGA specific optimizations was reimplemented using the NoGap Common Language (NoGapCL). The adder/subtracter implemented in Verilog can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12) as compared with the NoGap implementation which had a maximum operation frequency of 276 Mhz, using the hand optimized mantissa adder from the original Verilog code, the NoGap implementation reached timing closure at 326 Mhz.

As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.