Demo Data from SIGIR 2026 / reviewers in the wild / expert
Mike Gianfagna
dblp:39/6135
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design for manufacturability |
0.1 | 1 | 2006 | DFM: where's the proof of value? · DAC 2006 |
Electronic design automation › design for manufacturability › design for yield
yield enhancement |
0.0 | 1 | 2006 | DFM: where's the proof of value? · DAC 2006 |
Electronic design automation › hardware verification and test › hardware verification
complex system verification |
0.0 | 1 | 1994 | Panel: Complex System Verification: The Challenge Ahead · DAC 1994 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1994 | Panel: Complex System Verification: The Challenge Ahead · DAC 1994 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | DFM: where's the proof of value?abstractHow can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield).The aim of this panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results will be cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement).The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals. Shishpal Rawat, Raúl Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan |
DAC | 5 |
| 2005 | Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?abstractSeveral years ago, the vertically integrated semiconductor companies started to disaggregate into separate sectors, such as fabless, EDA, IP, Design Services, DFT, foundry, and test & packaging houses. On the one hand the disaggregated sectors are in the process of merging and optimizing their product lines, roles and responsibilities On the other hand, certain companies are trying to reverse the trend by reaggregating some of the disaggregated sectors. Will the reaggregation trend dominate? Which trend enables a better semiconductor market growth? Which trend allows superior technological offerrings? Who will be the shark? Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel |
DATE | 6 |
| 1994 | Panel: Complex System Verification: The Challenge AheadabstractNo abstract available. Ronald Collett, Mike Gianfagna, Michel Courtoy, Martin Baynes, Johan Van Ginderdeuren, Kenneth L. McMillan, Stephen Ricca, Alberto L. Sangiovanni-Vincentelli, Steve Sapiro, Naeem Zafar |
DAC | 2 |