Demo Data from SIGIR 2026 / reviewers in the wild / expert
Bohan Lan
dblp:393/6558
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0006-1488-3870ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 44% Electronic design automation · 44% Integrated circuit design · 13% | |
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis › public-key cryptography
modular multiplication |
0.9 | 1 | 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA · IEEE Trans. Computers 2025 |
Cryptographic primitives and cryptanalysis › public-key cryptography › modular multiplication
montgomery multiplication |
0.9 | 1 | 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA · IEEE Trans. Computers 2025 |
Electronic design automation › design optimization
area-time optimization |
0.9 | 1 | 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA · IEEE Trans. Computers 2025 |
Reconfigurable computing and FPGAs
FPGA arithmetic |
0.9 | 1 | 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA · IEEE Trans. Computers 2025 |
Integrated circuit design
digital circuit design |
0.3 | 1 | 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA · IEEE Trans. Computers 2025 |
Methods — techniques the papers use, named apart from their topics
dual-schedule · 1.7FIPS algorithm · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | MX-SE: Microscaling Data Format with Super Exponent for AI edge computing
Tianbo Ming, Yongjian Xu, Bohan Lan, Biwei Liu |
ISCAS | 3 |
| 2025 | FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGAabstractMontgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize$w$=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively. Yujun Xie 0001, Yuan Liu 0022, Xin Zheng 0001, Bohan Lan, Dengyun Lei, Dehao Xiang, Shuting Cai, Xiaoming Xiong |
IEEE Trans. Computers | 4 |