In the near future, personalized TV news programs should become a relevant method to access TV news. They will be produced from selecting and reordering "stories" contained in news programs. Automatic segmentation of news programs into story is an important step to reach this goal. We present a set rules for such segmentation. Methods for implementing these rules are based on image and sound analysis.

In this paper we present the abstract model of the Rapid-2 SIMD architecture. Rapid-2 is a low cost additional board for PCs. The abstract model is the basis for the design of a high level language, which is an extension of C. It includes new data types, with appropriate semantics. The L1 language enables co-specification of the board driver code and of Rapid-2 microcode. The L1 compiler was implemented. On a relevant application, the execution time of the microcode produced by the compiler is only 1.4 slower than that of handcoded microcode, while the development time is more than 10 times faster. Compiler improvements are still feasible.

The arbitrator device, or priority encoder, is necessary in associative memories because it enables to select one processing element among N by using a single instruction concerning all the data. It is a way to solve the problem of addressing a particular processor unit without an identification device. We first describe the solutions usually applied in associative memories. The binary arbitration tree reads the state of a flag in each processor and indicates which of them is the first set according to an order. We detail an improvement adapted to the architecture we are developing: an object-oriented paginated set-associative memory. This new arbitrator performs in parallel multiple sub-arbitrations within domains of consecutive elements. It allows parallel processing over arbitrary length data stored in the memory, and still has a modular and tree-like design suitable for VLSI implementation.>

The authors present RAPID a highly parallel processor which includes an extended relational algebra and text retrieval capacities in its instruction set. RAPID operates in parallel with the transfer of relevant data on the host machine bus, in a null apparent time. It is implemented with several copies of a specialized component using RISC (reduced-instruction-set-computer)-like technology, though its instructions are very high-level ones. It fully uses the resources of HCMOS3 technology and of full-custom design. A first version of the processor is presently being implemented.>

A new access method, based upon predicate-tree and previously presented in [GARD 83b, VALD 84, GARD 85], presents major possibilities of applications. The basic method which is implemented, allows the clustering of tuples from a relation when they satisfy some predicate. The aim of this paper, is to show the flexibility of this method and the numerous possibilities of extensions. In addition, to the permanent access paths based upon physical clustering, predicate-trees allow the implementation of classical secondary access paths. We give a method to code the values of several secondary attributes by use of secondary predicate-trees. This method requires a less important storage volume than classical secondary indexes. Predicate-trees can also efficiently speed up the join operation. Clustering information is used to limit the join to relevant pairs of partitions. Our evaluation shows that an improvement ratio of 7 or more versus traditional algorithms can be achieved.