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Sathyanarayanan Thammanur

dblp:40/3329 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Embedded and real-time systems · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
code generation
0.012004
A fast, memory-efficient register allocation framework for embedded systems · ACM Trans. Program. Lang. Syst. 2004
Compilers and program optimization
register allocation
0.012004
A fast, memory-efficient register allocation framework for embedded systems · ACM Trans. Program. Lang. Syst. 2004
Electronic design automation › high-level synthesis › resource binding
register allocation
0.012004
A fast, memory-efficient register allocation framework for embedded systems · ACM Trans. Program. Lang. Syst. 2004
Embedded and real-time systems › resource-constrained computing › resource-constrained embedded system
memory-constrained embedded systems
0.012004
A fast, memory-efficient register allocation framework for embedded systems · ACM Trans. Program. Lang. Syst. 2004

Methods — techniques the papers use, named apart from their topics

usage density analysis · 0.1live range analysis · 0.1linear scan · 0.1graph coloring · 0.1
YearPublicationVenuePosition
2004 A fast, memory-efficient register allocation framework for embedded systems
abstract
In this work, we describe a "just-in-time," usage density-based register allocator geared toward embedded systems with a limited general-purpose register set wherein speed, code size, and memory requirements are of equal concern. The main attraction of the allocator is that it does not make use of the traditional live range and interval analysis nor does it perform advanced optimizations based on range splitting but results in very good code quality. We circumvent the need for traditional analysis by using a measure of usage density of a variable. The usage density of a variable at a program point represents both the frequency and the density of the uses. We contend that by using this measure we can capture both range and frequency information which is essentially used by the good allocators based on splitting. We describe a framework based on this measure which has a linear complexity in terms of the program size. We perform comparisons with the static allocators based on graph coloring and the ones targeted toward just-in-time compilation systems like linear scan of live ranges. Through comparisons with graph coloring (Brigg's style) and live range-based (linear scan) allocators, we show that the memory footprint and the size of our allocator are smaller by 20% to 30%. The speed of allocation is comparable and the speed of the generated code is better and its size smaller. These attributes make the allocator an attractive candidate for performing a fast, memory-efficient register allocation for embedded devices with a small number of registers.
Sathyanarayanan Thammanur, Santosh Pande
ACM Trans. Program. Lang. Syst.1