One of the goals of much virtual reality (VR) research is to increase realism. In particular, many techniques for locomotion in VR attempt to approximate real-world walking. However, it is not yet fully understood how the design of more realistic locomotion techniques affects user task performance. We performed an experiment to compare a semi-natural locomotion technique (based on the Virtusphere device) with a traditional, non-natural technique (based on a game controller) and a fully natural technique (real walking). We found that the Virtusphere technique was significantly slower and less accurate than both of the other techniques. Based on this result and others in the literature, we speculate that locomotion techniques with moderate interaction fidelity will often have performance inferior to both high-fidelity techniques and well-designed low-fidelity techniques. We argue that our experimental results are an effect of interaction fidelity, and perform an analysis of the fidelity of the three locomotion techniques to support this argument.

Multi-class pattern classification has a variety of applications and could be achieved using artificial neural networks (ANN). There are two major system architectures for using ANNs in multi-class pattern classification: using a single ANN and using multiple ANNs. Independent of what architecture is used, one of the main concerns of using ANNs is that with increasing number of pattern classes and training datasets, the training time will increase dramatically which renders the ANN unfeasible. In this paper, the vast computational power of Graphics Processing Units (GPUs) is utilized to mitigate this problem. Different architectures and different methods of feeding pattern classes are implemented in a GPU platform. Different methods have been proposed to achieve maximum parallelism and subsequently maximize throughput. Our implementation exceeds the state-of-the-art in literature in terms of speed and the accurate use of GPU resources. As a result, the proposed approach's run time is about 75% shorter than the previous approaches. In multi-ANN architecture, due to the inherent parallelism in the proposed implementation, the execution time of a system for a digit recognition application is reduced from seven hours in CPU to about 4 seconds in GPU.

In recent years, parameter variations present critical challenges for manufacturability and yield on integrated circuits. In this paper, a new method for improving the timing yield of field programmable gate array (FPGA) devices affected by random and systematic within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations average critical path delay is reduced under conditions of large random and systematic variation considering spatial correlation. Compared to the previous approach which is limited to a fixed placement, our method improves timing yield by attempting several placements and routings without lengthy placement and routing phases to handle systematic variations and spatial correlation. The average critical path delay is reduced by 7% compared to the previous work over 20 MCNC benchmarks. General Terms: FPGA, process variation, placement, routing