The Samsung Exynos family of cores are highperformance “big” processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.

The recent deceleration of Moore's law bespeaks new approaches for optimization of resources. Machine learning has been applied to a wide variety of problems across multiple domains; however, the space of machine learning research for storage optimization is only lightly explored. In this paper, we focus on learning IO access patterns with the aim of improving the performance of flash based devices. Flash based storage devices provide orders of magnitude better performance than HDDs, but they suffer from high tail latencies due to garbage collection (GC) which causes variable IO latency. In flash devices, GC is the method of relocating existing data and deleting stale data, in order to create empty blocks for new incoming data. By learning the temporal trends of IO accesses, we built workload specific regression models for predicting the future time when the SSD will be in GC mode. We tested our models on synthetic traces (random read/write mix with fixed blocksize) generated by FIO workload generator. For the purpose of determining when the SSD is in GC mode, we track I/O completion times and classify completions that take more than 10 times the median completion value as representing those times when the SSD is in GC mode. Experiments run on the SSD models we tested reveal that a GC phase usually last 400 ms and it happens every 7000 ms on average. Results show that our workload specific models are accurate in predicting the time of next GC mode, achieving RMSE score of 10.61.

A slew-rate controlled, 800 Mbps voltage mode differential transmitter is presented here. An add-on, capacitive charge transfer based scheme is used to control output rise/fall times. The transmitter, designed and fabricated in a 65 nm CMOS technology, occupies an active area of 0.02 mm2and consumes 2.7 mW. Of this, the add-on slew-rate control occupies an area of 0.0027 mm, and consumes 0.5 mW.

A low power, high speed (480 Mbps) envelope detector for serial data systems such as USB2.0 is presented in this paper. The proposed architecture is based on a high frequency rectifier implementation along with a comparator and offers about 50% power and area saving compared to prior implementations using multiple comparators. A calibration scheme to make the envelope detector process, voltage and temperature independent is discussed. This architecture can be used for any high frequency serial interface requiring envelope detection. The circuit is implemented in 45 mn CMOS technology and consumes 2.5 mW power and occupies 0.015 mm2area.