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Hannes Weissteiner

dblp:400/5248 · DBLP profile ↗
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8ranked-venue papers
2as first author
8since 2021 · last 2026
0009-0006-0129-4073ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 8 · 2 first-author · 8 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
4 papers
Hardware security and side channels · 90% Systems and software security · 10%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 61% Hardware reliability and fault tolerance · 31% Performance modeling and evaluation · 8%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
trusted execution environments
2.032025
TEEcorrelate: An Information-Preserving Defense against Performance-Counter Attacks on TEEs · USENIX Security Symposium 2025
TDXploit: Novel Techniques for Single-Stepping and Cache Attacks on Intel TDX · USENIX Security Symposium 2025
CounterSEVeillance: Performance-Counter Attacks on AMD SEV-SNP · NDSS 2025
Hardware security and side channels
side-channel attack
1.922026
Continuous User Behavior Monitoring using DNS Cache Timing Attacks · NDSS 2026
CounterSEVeillance: Performance-Counter Attacks on AMD SEV-SNP · NDSS 2025
Hardware security and side channels › microarchitectural attacks
performance counter attacks
1.722025
TEEcorrelate: An Information-Preserving Defense against Performance-Counter Attacks on TEEs · USENIX Security Symposium 2025
CounterSEVeillance: Performance-Counter Attacks on AMD SEV-SNP · NDSS 2025
Hardware security and side channels › side-channel attack › cache side-channel attacks
cache timing attack
1.012026
Continuous User Behavior Monitoring using DNS Cache Timing Attacks · NDSS 2026
Systems and software security
user behavior monitoring
1.012026
Continuous User Behavior Monitoring using DNS Cache Timing Attacks · NDSS 2026
Memory systems
DRAM
1.012026
Memory Band-Aid: A Principled Rowhammer Defense-in-Depth · NDSS 2026
Hardware reliability and fault tolerance
memory reliability
1.012026
Memory Band-Aid: A Principled Rowhammer Defense-in-Depth · NDSS 2026
Memory systems › DRAM
rowhammer
1.012026
Memory Band-Aid: A Principled Rowhammer Defense-in-Depth · NDSS 2026
Hardware security and side channels › microarchitectural attacks
cache attacks
0.912025
TDXploit: Novel Techniques for Single-Stepping and Cache Attacks on Intel TDX · USENIX Security Symposium 2025
Hardware security and side channels › trusted execution environments
Intel TDX
0.912025
TDXploit: Novel Techniques for Single-Stepping and Cache Attacks on Intel TDX · USENIX Security Symposium 2025
Hardware security and side channels › fault attacks
single-stepping attack
0.912025
TDXploit: Novel Techniques for Single-Stepping and Cache Attacks on Intel TDX · USENIX Security Symposium 2025
Hardware security and side channels › trusted execution environments
AMD SEV-SNP
0.312025
CounterSEVeillance: Performance-Counter Attacks on AMD SEV-SNP · NDSS 2025
Performance modeling and evaluation › performance monitoring
hardware performance counters
0.312025
TEEcorrelate: An Information-Preserving Defense against Performance-Counter Attacks on TEEs · USENIX Security Symposium 2025

Methods — techniques the papers use, named apart from their topics

information-preserving defense · 1.7DNS cache timing · 1.0defense mechanisms · 0.9defense mechanism · 0.9cache side channel · 0.9
YearPublicationVenuePosition
2026 TELESCOPE: TDX Exploit Leaking Encrypted Data using Sibling Core Performance Counters
abstract
Trusted execution environments (TEEs) protect applications running inside of them from untrusted host systems. The host can not access or modify the memory of applications protected by a TEE. Intel TDX is a recently introduced TEE that allows for the execution of arbitrary code, including entire operating systems, inside a protected environment. Prior work has attacked AMD SEV-SNP, AMD's counterpart to Intel TDX, using performance counters, by leaking sensitive information through them, e.g., which branches are taken. Intel TDX is thought not to be affected by such attacks, as it disables performance counters when entering the protected guests (TDs) to mitigate these attacks.
Fabian Rauscher, Hannes Weissteiner, Daniel Gruss
AsiaCCS2
2026 Memory Band-Aid: A Principled Rowhammer Defense-in-Depth
Carina Fiedler, Jonas Juffinger, Sudheendra Raghav Neela, Martin Heckel, Hannes Weissteiner, A. Giray Yaglikçi, Florian Adamsky, Daniel Gruss
NDSS5
2026 Continuous User Behavior Monitoring using DNS Cache Timing Attacks
Hannes Weissteiner, Roland Czerny, Simone Franza, Stefan Gast, Johanna Ullrich, Daniel Gruss
NDSS1
2025 The HMB Timing Side Channel: Exploiting the SSD's Host Memory Buffer
Jonas Juffinger, Hannes Weissteiner, Thomas Steinbauer, Daniel Gruss
DIMVA (1)2
2025 Epistemology of Rowhammer Attacks: Threats to Rowhammer Research Validity
Martin Heckel, Hannes Weissteiner, Florian Adamsky, Daniel Gruss
ESORICS (3)2
2025 CounterSEVeillance: Performance-Counter Attacks on AMD SEV-SNP
Stefan Gast, Hannes Weissteiner, Robin Leander Schröder, Daniel Gruss
NDSS2
2025 TDXploit: Novel Techniques for Single-Stepping and Cache Attacks on Intel TDX
Fabian Rauscher, Luca Wilke, Hannes Weissteiner, Thomas Eisenbarth 0001, Daniel Gruss
USENIX Security Symposium3
2025 TEEcorrelate: An Information-Preserving Defense against Performance-Counter Attacks on TEEs
Hannes Weissteiner, Fabian Rauscher, Robin Leander Schröder, Jonas Juffinger, Stefan Gast, Jan Wichelmann, Thomas Eisenbarth 0001, Daniel Gruss
USENIX Security Symposium1