Representative Sampling, exemplified by SimPoint is widely utilized in pre-silicon performance evaluation. It relies on the code signature to characterize programs and select representative simulation points to estimate the performance. Several code signatures have been proposed, including BBV, MIC, BBV-LDV, and PMC. Although these code signatures can achieve low average performance estimation errors for benchmark suites, they still yield high errors for specific programs within those suites, due to their inherent limitations of incomplete characteristic representations and indirect performance correlations. In this work, we propose the utilization of mechanistic micromodel signatures, MeMo, to enhance representative sampling. MeMo contains various signatures sourced from a series of micromodels under different configurations. These models encompass fetch, issue, and cache models, each concentrating on certain$\mu$Arch structure constraints while idealizing the others. MeMo enables the comprehensive depiction of different program characteristics and their performance responses while not confined to specific$\mu$Arch. We thoroughly evaluated MeMo against current code signatures on SPEC CPU2017. The experiment demonstrated that compared to the most commonly utilized BBV, MeMo can substantially reduce the average CPI estimation error from 3.96% to 1.63% and significantly suppress the maximum estimation error from 19.94% to 6.49%.

Binary translation enables transparent execution, analysis, and modification of the binary program, serving as a core technology that facilitates instruction set emulation, cross-platform compatibility of software, and program instrumentation. Handling indirect branch instructions is widely recognized as a significant performance bottleneck in binary translation. While the target of a direct branch can be determined during the translation phase, an indirect branch requires a runtime lookup from the guest program counter to the host program counter, significantly influencing the performance of translator. Although several methods have been proposed to accelerate this process, each guest indirect branch instruction still translates into approximately 10 host instructions, resulting in considerable overhead. This article introduces Tiaozhuan, which addresses this issue by employing two optimization schemes. First, full address mapping uses a larger address space to store address mappings from guest to host, effectively reducing the number of instructions required to lookup the target of an indirect branch. Second, exceptionassisted branch elimination further eliminates branch instructions that check target correctness of targets in the lookup process. These two approaches enable indirect branches target lookup to be completed within one to two instructions, noticeably decreasing the overhead of indirect branches. Compared to state-of-the-art mechanisms, the SPEC CPU2006 benchmark suite showed a reduction in the number of instructions by an average of 4.2%, with the highest observed performance improvement reaching 19.4% and an average increase of 3.9%.