Demo Data from SIGIR 2026 / reviewers in the wild / expert
Leo Hellerman
dblp:41/6094
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 1974
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 5 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Performance modeling and evaluation · 36% Electronic design automation · 31% Emerging computing paradigms · 21% | |
| Theoretical computer science
2 papers |
Information theory · 54% Automata and formal languages · 46% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 8 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Operating systems › resource management
memory management |
0.0 | 1 | 1968 | Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968 |
Emerging computing paradigms › neuromorphic computing
associative memory |
0.0 | 1 | 1968 | Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1963 | A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits · IEEE Trans. Electron. Comput. 1963 |
Electronic design automation › logic synthesis
logic minimization |
0.0 | 1 | 1963 | A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits · IEEE Trans. Electron. Comput. 1963 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1963 | A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits · IEEE Trans. Electron. Comput. 1963 |
Automata and formal languages › finite automata › sequential machines
sequential circuits |
0.0 | 1 | 1966 | Continuity and Realizability of Sequence Transformations · IEEE Trans. Electron. Comput. 1966 |
Processor architecture and microarchitecture › microprogramming
control store |
0.0 | 1 | 1968 | Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968 |
Processor architecture and microarchitecture
microprogramming |
0.0 | 1 | 1968 | Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
information-theoretic measures · 0.0information-theoretic measure · 0.0read-only control storage · 0.0logic minimization · 0.0curtis-hedlund-lyndon theorem · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1974 | A Discussion of "A Measure of Computational Work"abstractThis note presents a discussion of some issues that have been raised about my paper1"A Measure of Computational Work." Leo Hellerman |
IEEE Trans. Computers | 1 |
| 1972 | A Measure of Computational WorkabstractThe computational work of a process is measured in terms of the information in a memory for its table-lookup implementation. This measure is applied first to simple logical and arithmetic processes, and then more complicated processes comprising organizations (called synergisms) of several subprocesses. The computational advantages of Cartesian, compositional, and sequential synergisms are investigated and illustrated by means of the work measure. The relation between the work of a process and the work capacity of a facility on which it is implemented is examined, and a concept of efficiency of implementations is formulated. A few areas for further investigation are outlined. Leo Hellerman |
IEEE Trans. Computers | 1 |
| 1968 | Control Storage Use in Implementing an Associative Memory for a Time-Shared ProcessorabstractAbstract—The Cambridge System, comprising a standard IBM System/360 Model 40 and an associative memory, is described from the viewpoint of its implementation using the READ-only control storage of the Model 40. In particular, we discuss the use of the ROS in 1) controlling the flow of data between the CPU and the associative memory registers, and 2) handling translation control, absent page indications, and variable field operand pretesting, when the associative memory is used for page translation in a time-sharing mode of operation. Although the main use of the system is as a computer facility that may be shared simultaneously by up to fifteen users, it may also be used as an ordinary batch processor having a small experimental associative memory among its facilities. The magnitude of the ROS additions and modifications, in terms of numbers of microinstructions, is given. Leo Hellerman, Gerhard E. Hoernes |
IEEE Trans. Computers | 1 |
| 1966 | Continuity and Realizability of Sequence TransformationsabstractIn this paper we study some relations between the continuity of sequence transformations and their realizability by logic nets. The main results discussed include: the Curtis-Hedlund-Lyndon theorem which states that, if a sequence transformation is continuous and unitary (commutative with the shift transformation), then it can be realized by a net without feedback, and, the extension of this theorem to the finitary case. We find that unitary transformations are realized by definite automata, and finitary transformations are realized by indefinite automata. The term ``automata'' is used here in a modification of its usual sense, and we explore the relation between the conventional and modified notions. Many of the concepts and more significant mathematical results in this report can be found in another context in works by Hedlund and others. What may be new and of interest to computer scientists, we believe, is their application to the theory of sequential circuits. Leo Hellerman, William L. Duda, Shmuel Winograd |
IEEE Trans. Electron. Comput. | 1 |
| 1963 | A Catalog of Three-Variable Or-Invert and And-Invert Logical CircuitsabstractThis report gives a complete catalog of minimal NOR circuits and minimal NAND circuits, assuming complements not available, for all logic functions of three variables. Minimal circuits for a function are those that satisfy these conditions: 1) The number of logic blocks of the circuit is least possible for performing the function; 2) The number of connections in the circuit (total number of inputs) is least possible, subject to the condition that the circuit satisfies the first condition. In addition, the circuits satisfy certain reasonable restrictions on fan-in and fan-out. Leo Hellerman |
IEEE Trans. Electron. Comput. | 1 |