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Qilong Di

dblp:415/6252 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet of things and sensor networks · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet of things and sensor networks
backscatter communication
0.912025
Inductor-Free LoRa Backscatter · IEEE Trans. Netw. 2025
Internet of things and sensor networks › backscatter communication
lora backscatter
0.912025
Inductor-Free LoRa Backscatter · IEEE Trans. Netw. 2025
Integrated circuit design
analog and mixed-signal circuits
0.912025
Inductor-Free LoRa Backscatter · IEEE Trans. Netw. 2025

Methods — techniques the papers use, named apart from their topics

virtual impedance · 1.7oversampling · 1.7
YearPublicationVenuePosition
2025 Inductor-Free LoRa Backscatter
abstract
LoRa backscatter achieves long-range communication at the cost of only tens of micro-watts of power when implemented in integrated circuits (ICs), which makes it a potential enabler for massive IoT. However, despite the above advantages, we find that the current tag design wastes approximately 72% of the chip functional area due to the use of large-size inductors in the impedance loads array. This inefficiency significantly increases the cost per chip during mass production. To address this die area issue, we propose OsTAG, a novel LoRa backscatter design that eliminates all inductors in the impedance loads array while maintaining the same quantization resolution. The key innovation lies in the creation of virtual impedance using oversampling. Realizing such design requires overcoming the technical challenges of mitigating approximation error and managing oversampling clock imperfections. To validate our design, we develop prototype and an IC, demonstrating promising results in terms of both performance and efficiency. OsTAG is expected to cost only 28% of the existing chip area while achieving comparable hundred-meter level communication range.
Fengyuan Zhu 0001, Jiaquan He, Jiajun Lin, Qilong Di, Meng Jin 0002, Xiaohua Tian
IEEE Trans. Netw.6