Wireless MIMO communication systems nowadays are driven by the requirement to minimize the hardware computational complexity of detection algorithms while preserving high detection performance. To address this challenge, traditional tree-based approaches like the K-best algorithm have been proposed, which employ a fixed complexity at each layer to manage computational demands. The K-best algorithm remains computationally intensive due to its complexity highly dependent on the QAM modulation size and is further followed by a sorting scheme applied at each layer. Another tree-based approach, called the box decoding, has been developed to overcome these limitations in small-scale MIMO systems. However, the complexity of this algorithm escalates significantly in MIMO systems with higher dimension as the number of candidates generated by the box decoding grows substantially. In this paper, we propose an innovative solution, called the K-box algorithm. In contrast to K-best, K-box decouples the candidate selection procedure and the size of constellation space similar to box decoding while restraining the candidates expansion in higher-dimensional MIMO by sorting only when the number of candidates exceed a certain limit. Testing on 4 × 4 and 8 × 8 64-QAM systems for 5G new radio (NR) link demonstrates SNR gains of 0.6 dB at a BER of 10−2compared to the K-best algorithm, while achieving 77% and 76% complexity reduction in partial Euclidean distance (PED) computations and sorting complexity reductions of 94% and 92% respectively.

A surge of reduced capability and low-cost devices under the 5G framework for many Internet of Things (IoT) applications is foreseen. The new 3GPP standard, NR REDCAP, provides the means to develop such devices. However, keeping these inexpensive devices synchronized with the 5G network requires continuous synchronization algorithms running parallel with the receiver processing. Our analysis and literature agree that the acceleration of these algorithms on Single Instruction Multiple Data (SIMD) architectures is challenging because of the data dependencies in the recursive filter that is usually employed in synchronization algorithms and hence, requires a significant computing budget. The consequent need for activating extra hardware to perform continuous synchronization leads to rising device cost and higher power consumption which is undesirable. In this work, we address this problem by proposing an implementation that efficiently vectorizes the synchronization algorithm, including the recursive filter, on a wide SIMD vector DSP. The results show that the proposed implementation achieves a speedup of 9X over scalar processing. Subsequently, the synchronization kernel can run on a limited MHz budget of the vector DSP.

Generalised frequency division multiplexing (GFDM) is a novel multicarrier waveform with reduced out- of-band emission and peak-to-average-power-ratio compared to orthogonal frequency division multiplexing. Due to these properties, GFDM is regarded a candidate waveform for future wireless communication. However, an implementation that addresses operating conditions of handheld devices has not yet been considered. We propose a software programmable GFDM solution for handheld devices. This paper presents necessary capabilities of a vector DSP implementation to efficiently process GFDM in the context of 5G use cases. We investigate structural properties and numerical precision of the GFDM algorithm, propose a scalable vectorised approach for single instruction multiple data processing, and carry out a performance-cost evaluation. We present our key findings to enable GFDM functionality on handheld user equipment.

We explore the potential of subsystem-based design to reduce cost and time-to-market in the design of advanced Systems-on-Chips (SoCs) while retaining low-power and high performance processing. Using a concrete audio subsystem as an example, we illustrate the benefits of modular SoC integration with subsystems and identify challenges to be addressed. Well-designed subsystems pre-integrate hardware and software modules to implement complete system functions and offer high-level hardware and software interfaces for easy SoC integration. Configurability of subsystems enables reuse across SoCs. Subsystems can offer software plug-ins to support integration into a software stack on a host processor while making core crossings transparent for the application programmer. We conclude that subsystems can indeed be the next reuse paradigm for efficient SoC integration.

In this paper we study the requirements on processors for implementing the different system functions of a System-on-Chip (SoC). We illustrate the impact of architecture and implementation choices on processor performance and power consumption. We conclude that a palette of processor technologies is required for building advanced SoCs that meet constraints on power consumption.

Advanced SoCs integrate a diverse set of system functions that pose different requirements on the SoC infrastructure. Predictable integration of such SoCs, with guaranteed Quality-of-Service (QoS) for the real-time functions, is becoming increasingly challenging. We present a structured approach to predictable integration based on a combination of architectural principles and associated analysis techniques. We identify four QoS classes and define the type of QoS guarantees to be supported for the two classes targeted at real-time functions. We then discuss how a SoC infrastructure can be built that provides such QoS guarantees on its interfaces and how network calculus can be applied for analyzing worst-case performance and sizing of buffers. Benefits of our approach are predictable performance and improved time-to-market, while avoiding costly over-design.

We propose (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where σ bounds the traffic burstiness and ρ the traffic rate. This regulation changes the burstiness and timing of traffic flows, and can be used to decrease delay and reduce buffer requirements in the SoC infrastructure. In this paper, we define and analyze the regulation spectrum, which bounds the upper and lower limits of regulation. Experiments on a Network-on-Chip (NoC) with guaranteed service demonstrate the benefits of regulation. We conclude that flow regulation may exert significant positive impact on communication performance and buffer requirements.

Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-XACT standards and demonstrate how these standards are deployed in three industrial IP integration flows. Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e. IP-XACT based verification software generation and IP-XACT based configuration of debug environments. We conclude that IP-XACT is enabling powerful IP integration methodologies and that future extensions can further increase the effectiveness of IP-XACT standards.

This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.

Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large storage capacity and high bandwidth while data accesses can be irregular. The SoC architectures used for implementing these applications typically contain a heterogeneous collection of processing elements and use a single interface to off-chip DRAM in order to provide the required storage capacity at a low cost. Proper integration of interconnect and memory architecture is required to achieve the required bandwidths and latencies for accessing memory. The application requirements as well as the characteristics and constraints for accessing memory are key inputs for NoC design. Future memory technologies may cause a paradigm shift by offering high-bandwidth memory access, possibly via multiple memory interfaces.

In shared-memory multi-processor Systems on Chip for media processing, the access to off-chip memory is often a critical resource. The memory channel is shared by a mix of streams with timing requirements at different levels. The streams are arbitrated in the memory access network. Some streams have to meet a hard deadline for each transaction; other streams have to meet task-level execution-time constraints, where task execution times depend on the service received when performing memory accesses. Earlier work has resulted in arbitration algorithms that provide the necessary balance between the different stream types, allowing aggressive system design with a high utilization of the memory access path. The next challenge is to provide real-time analysis in an early stage of system design. To address this challenge, this paper proposes a practical approach that combines proven analytical methods with fast simulations. The approach provides a design space from which to choose arbiter settings and buffer sizes for memory-communication buffers.

Presents and evaluates the SPADE (System level Performance Analysis and Design space Exploration) methodology through an illustrative case study. SPADE is a method and tool for architecture exploration of heterogeneous signal processing systems. In this case study we start from an M-JPEG application and use SPADE to evaluate alternative multiprocessor architectures for implementing this application. SPADE follows the Y-chart paradigm for system level design; application and architecture are modeled separately and mapped onto each other in an explicit design step. SPADE permits architectures to be modeled at an abstract level using a library of generic building blocks, thereby reducing the cost of model construction and simulation. The case study shows that SPADE supports efficient exploration of candidate architectures; models can be easily constructed, modified and simulated in order to quickly evaluate alternative system implementations.

We present a programming interface called YAPI to model signal processing applications as process networks. The purpose of YAPI is to enable the reuse of signal processing applications and the mapping of signal processing applications onto heterogeneous systems that contain hardware and software components. To this end, YAPI separates the concerns of the application programmer, who determines the functionality of the system, and the system designer, who determines the implementation of the functionality. The proposed model of computation extends the existing model of Kahn process networks with channel selection to support non-deterministic events. We provide an efficient implementation of YAPI in the form of a C++ run-time library to execute the applications on a workstation. Subsequently, the applications are used by the system designer as input for mapping and performance analysis in the design of complex signal processing systems. We evaluate this methodology on the design of a digital video broadcast system-on-chip.

We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a core, its design must be supplemented with on-chip co-processors to obtain a cost-effective system. Good performance is obtained through a uniform 64-bit 5 issue-slot VLIW design, supporting subword parallelism with an extensive instruction set optimized with respect to media-processing. Multi-slot 'super-ops' allow powerful multi-argument and multi-result operations. As an example, the IDCT algorithm shows a very low instruction count in comparison with other processors. To achieve good performance, critical sections in the application program source code need to be rewritten with vector data types and function calls for media operations. Benchmarking with several media applications was used to tune the instruction set and study cache behaviour. This resulted in a VLIW architecture with wide data paths and relatively simple CPU control.

The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. The new vector operations and superoperations need to be supported by the compiler and simulator to make them accessible to application programmers. It was our intention to support these new features while remaining compliant with the ANSI C standard. This paper describes the mechanisms which were implemented to achieve this goal. Furthermore, the optimization of applications needs to address the vectorization of the functions to be implemented. Some general guidelines for producing efficient vectorized code are given.

In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a quantitative way and therefore supports him in the design process to find better performing architectures. The context of our work is video signal processing algorithms which are mapped onto weakly-programmable, coarse-grain dataflow architectures. The algorithms are represented as Kahn graphs with the functionality of the nodes being coarse-grain functions. We have implemented an architecture simulation environment that permits the definition of dataflow architectures as a composition of architecture elements, such as functional units, buffer elements and communication structures. The abstract, clock-cycle accurate simulator has been built using a multi-threading package and employs object oriented principles. This results in a configurable and efficient simulator. Algorithms can subsequently be executed on the architecture model producing quantitative information for selected performance metrics. Results are presented for the simulation of a realistic application on several dataflow architecture alternatives, showing that many different architectures can be simulated in modest time on a modern workstation.

In this paper we present a user interface that supports design engineers in having efficient interaction with their CAD system. We adopt a flow-based paradigm for design history browsing and tool selection. Based on this paradigm the user interface shows design objects in the context of executed-, enabled- and disabled tools and related design objects. We present a flow coloring algorithm which is used by the user interface to automatically select convenient doses of information related to a user-specified design object. The user interface integrates many aspects of user interaction into a single platform that enables design engineers to efficiently execute the design cycle. This includes tool invocation facilities, an intuitive mechanism for interaction among different browsers, and a mechanism for automatic updates of the information that is being displayed as changes occur. The user interface has been implemented as a desktop facility in the Nelsis CAD Framework.

An attempt to realize an integrated design environment with a maximum of functionality and an absolute minimum impact on existing design tools is discussed. Addressed are the interface between the design tools and the framework, the architecture of the framework including the interrelations among the different components, and the internal operation of the flow management components. These issues are combined to arrive at an overall solution that yields a running design flow management system implemented in the NELSIS CAD framework. The net result is a CAD system that makes the graphical representation of the design tasks the basis for all design actions. The system provides generic mechanisms applicable to many application domains, and thus new tools can be easily incorporated.>

In this paper a new approach for design jlow management is presented.We describe how the inputlouput relations between tools can be defined in a j%nwnap.For this, several concepts are introduced, such as defiing activities for tools, run-time activity identification, hierarchical jlow graphs, modijkation versus extension, and the possibility to have loops in the j?owmap.We also address tool scheduling and the integration of design Jow management in the architecture of afiarne-bared &sign system.

A key aspect of a CAD framework is the management of meta data, i.e. high level information about the structure and status of the design.In this paper we present the architecture of a modular frame-based IC design system and elucidate the software structure adopted for the management of meta data in its CAD framework.The meta data management software module is efficient, operates in a distributed hardware environment, controls concurrent access, and offers a high level query interface for meta data browsing.