Demo Data from SIGIR 2026 / reviewers in the wild / expert
Qiangsheng Su
dblp:421/2313
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0008-2125-9616ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Storage systems · 58% Memory systems · 42% | |
| Databases, data mining, and information retrieval
1 paper |
Indexing and storage engines · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › indexing › index structure
hashing index |
1.0 | 1 | 2026 | Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory · HPCA 2026 |
Storage systems
key-value storage |
1.0 | 1 | 2026 | Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory · HPCA 2026 |
Memory systems
memory disaggregation |
1.0 | 1 | 2026 | Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory · HPCA 2026 |
Indexing and storage engines
hash index |
0.9 | 1 | 2025 | MetoHash: A Memory-Efficient and Traffic-Optimized Hashing Index on Hybrid PMem-DRAM Memories · SC 2025 |
Indexing and storage engines › hash index
persistent memory hash index |
0.9 | 1 | 2025 | MetoHash: A Memory-Efficient and Traffic-Optimized Hashing Index on Hybrid PMem-DRAM Memories · SC 2025 |
Memory systems
non-volatile memory |
0.9 | 1 | 2025 | MetoHash: A Memory-Efficient and Traffic-Optimized Hashing Index on Hybrid PMem-DRAM Memories · SC 2025 |
Storage systems
storage reliability |
0.3 | 1 | 2026 | Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory · HPCA 2026 |
Methods — techniques the papers use, named apart from their topics
three-layer index structure · 1.7fingerprinting · 1.7bucket relocation · 1.7doorbell batching · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated MemoryabstractBy decoupling compute and memory resources into independent pools that are provisioned and managed separately, disaggregated memory (DM) is promising to break the scaling constraints for memory systems and improve resource utilization. However, it also comes with a new challenge to design a high-performance hashing index to manage the vast memory pool with weak computing power. In this paper, we reconsider this problem and find that existing hashing indexes for DM still experience two fundamental yet unresolved limitations: (i) amplifying traffic under high insertion concurrency, and (ii) introducing significantly high insertion latency, stemming mainly from the directory synchronization and item relocation in resizing process. We resolve the above limitations by designing Pulse, a finegrained hierarchical hashing index for DM. Pulse comprises the following three design primitives. It proposes a multi-level index structure, which breaks the conventional flat directory into multiple sub-directories that are organized hierarchically, achieving fine-grained directory synchronization. Pulse also maintains a small portion of hashed keys in the memory pool, which aids in item relocation during resizing, thereby reducing resizing traffic and promising system stability. Pulse finally exploits operation parallelism by tailoring the doorbell batching mechanism with selective signaling. We conduct extensive experiments using a variety of benchmarks, showing that Pulse can improve$3.46 \times$of the throughput and reduce 76.3% of the tail latency compared to state-of-the-art hashing indexes. Guangyang Deng, Zixiang Yu, Zhirong Shen, Qiangsheng Su, Zhinan Cheng, Jiwu Shu |
HPCA | 4 |
| 2026 | Breaking Barriers in Atomic Scaling: A Hardware-Software-Collaborated Framework to Deconstruct RDMA Atomic
Guangyang Deng, Qiangsheng Su, Zhirong Shen, Qing Wang 0031, Yina Lv, Ronglong Wu, Jiwu Shu |
ISCA | 2 |
| 2025 | MetoHash: A Memory-Efficient and Traffic-Optimized Hashing Index on Hybrid PMem-DRAM MemoriesabstractPersistent memory (PMem) brings new design considerations in realizing high-performance and scalable hashing indexes. We uncover that existing hashing indexes for PMem still suffer from traffic amplification and memory inefficiency. We present MetoHash, a memory-efficient and traffic-optimized hashing index on hybrid PMem-DRAM memories. MetoHash proposes a three-layer index structure spanning across CPU caches, DRAM, and PMem for data management. It aggregates the incoming key-value items in CPU caches for fast inserts, which are then arranged in DRAM and flushed to PMem, to eliminate traffic amplification. MetoHash also uses fingerprinting to reduce unnecessary probings over PMem and removes duplicate items during bucket relocations. We implement MetoHash on PMem with persistent and volatile CPU caches, and show that compared to state-of-the-art hashing indexes for PMem, MetoHash improves the throughput by 86.1–257.6% under various workloads. Zixiang Yu, Guangyang Deng, Zhirong Shen, Qiangsheng Su, Ronglong Wu, Xiaoli Wang 0002, Quanqing Xu, Chuanhui Yang, Zhifeng Bao |
SC | 4 |