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Xijia Yao

dblp:425/6713 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0001-4105-6161ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 77% Processor architecture and microarchitecture · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › sparse linear algebra
sparse matrix multiplication
1.012026
ASM-SpMM: Unleashing the Potential of Arm SME for Sparse Matrix Multiplication Acceleration · PPoPP 2026
Processor architecture and microarchitecture › instruction set architecture
instruction set extension
0.312026
ASM-SpMM: Unleashing the Potential of Arm SME for Sparse Matrix Multiplication Acceleration · PPoPP 2026

Methods — techniques the papers use, named apart from their topics

architecture-aware optimization · 1.0
YearPublicationVenuePosition
2026 ASM-SpMM: Unleashing the Potential of Arm SME for Sparse Matrix Multiplication Acceleration
abstract
Sparse Matrix–Matrix Multiplication (SpMM) is a core kernel in scientific computing, data analytics, and artificial intelligence, supporting applications such as linear solvers and Graph Neural Networks (GNNs). The Scalable Matrix Extension (SME) in Armv9 introduces dedicated matrix acceleration for ARM CPUs, but exploiting its full potential for SpMM requires architecture-aware optimizations to address irregular sparsity and hardware constraints.
Jiazhi Jiang, Xijia Yao, Jinhui Wei, Dan Huang 0001, Yutong Lu
PPoPP2