Demo Data from SIGIR 2026 / reviewers in the wild / expert
Hanyu Wen
dblp:437/0376
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0000-0580-142XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
1.0 | 1 | 2026 | Analog Mixed-Signal Circuit Splitting and Defect Simulation Method Based on Signal Flow Diagram · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Electronic design automation › hardware verification and test
testability improvement |
0.3 | 1 | 2026 | Analog Mixed-Signal Circuit Splitting and Defect Simulation Method Based on Signal Flow Diagram · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Methods — techniques the papers use, named apart from their topics
signal flow diagram · 1.0parallel defect simulation · 1.0graph analysis · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Analog Mixed-Signal Circuit Splitting and Defect Simulation Method Based on Signal Flow DiagramabstractComprehensive defect simulation in the integrated circuit design stage is the basic guarantee to improve testability, which is also the basic requirement of current automotive-grade chip design. For example, there are 6 types of basic defect models for a single MOS transistor in a circuit, and the defect set of analog/hybrid integrated circuits containing thousands of devices is extremely large. It is very time-consuming to inject a large number of defects one by one and solve them in a large-scale matrix. In fact, the complete defect simulation often takes months or even years, and there is no good solution at present. In this paper, a circuit splitting method based on signal flow and graph analysis is proposed, which models the control relationship between the device current and voltage nodes of the circuit with a directed dependency graph through signal flow analysis. Then, more weak connections are obtained by identifying and breaking the feedback loops of larger strongly connected components, and the weak connectivity in strongly connected components are split to realize circuit splitting. The acceleration can then be achieved by parallel defect simulation. At the same time, in order to investigate the observability of the internal defects in the previous strongly connected components in the subsequent strongly connected components, the defects were simulated according to the one-way transfer relationship between each strongly connected components in directed acyclic graph. The equivalent compression method of the defects and the signal in the transfer process is proposed, which reduces the number of simulation times of the defects. Finally, this paper takes the benchmark circuit Bandgap, LDO and SARADC circuits as examples, and uses HSPICE simulation to verify the effectiveness of the graph splitting method. Compared with the latest transistor level circuit splitting scheme, the circuit splitting algorithm proposed in this paper can split more and smaller circuit blocks. Using the circuit blocks we have divided to implement the parallel defect simulation scheme and the defect transfer simulation scheme is more effective than the traditional full-circuit and full-defect simulation one by one. Hanyu Wen, Xinhong Huang, Qihao Zhang, Haitao Fu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |