This paper presents a novel low power 11-bit hybrid ADC using flash and delay line architectures, where a 4-bit flash ADC is followed by a 7-bit delay-line ADC. This hybrid ADC inherits accuracy and power efficiency from flash ADCs and delay-line ADCs, respectively. Also, in order to reduce the power of the first stage flash ADC, a power-saving technique is adopted by biasing the DC tail current of the preamplifiers at 5μA instead of the operational current, 47μA in stand-by mode. The hybrid ADC was designed and simulated in a commercial 65nm process. With 1.1 V supply and 100 MS/s, the ADC achieves an SNDR of 60 dB and consumes 1.6 mW, which results in a figure of merit (FOM) of 19.4 fJ/conversion-step without any calibration technique. Also, Monte Carlo simulations are performed with a 3σ device mismatch for the SNDR estimation, and the SNDR is observed to be better than 58.5 dB.

Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. This strongly supports the scalability of delay line ADCs and their improved performance in further scaled fabrication processes.

In this paper, we present an agglomeratively multilevel floorplanning/placement framework based on the B -tree representation called MB- tree to handle the floorplanning and packing for large-scale building modules. The MB-tree adopts a two-stage technique, i.e., clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B -tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB-tree preserves the geometric relations among modules during declustering, which makes the MB-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, the MB-tree scales very well as the circuit size increases.

We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroups a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.

Article Free Access Share on Feasible two-way circuit partitioning with complex resource constraints Authors: Hsun-Cheng Lee Department of Information and Computer Engineering, Chung Yuan Christian University, Chungli, Taiwan Department of Information and Computer Engineering, Chung Yuan Christian University, Chungli, TaiwanView Profile , Ting-Chi Wang Department of Information and Computer Engineering, Chung Yuan Christian University, Chungli, Taiwan Department of Information and Computer Engineering, Chung Yuan Christian University, Chungli, TaiwanView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 435–440https://doi.org/10.1145/368434.368731Published:28 January 2000Publication History 0citation93DownloadsMetricsTotal Citations0Total Downloads93Last 12 Months4Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF