The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead.>

Abstract : The proposed memory consists of a normal word line over a strip of magnetic film and a digit line split into three parallel conductors. Writing is accomplished using the standard method of coincidence of transverse and digit fields (all three digit conductors are excited equally). The result is a region at the intersection which is magnetized either to the right for a ONE or to the left for a ZERO. To interrogate the memory in all bits simultaneously, the middle digit conductors alone are excited with a field to the left, if searching for a ZERO, and with a field to the right, if searching for a ONE. For either match condition, there will be essentially no change in the magnetization of the interrogated cell. For a mismatch, the magnetization will rotate noncoherently to the multidomain pattern which occurs just below nucleation. It is proposed that the magnetoresistive effect be used to sense the mismatch condition. Experimentally, it is found that a resistance change corresponding to approximately 10 per cent of that for full transverse switching is obtained.