Industry 4.0 offers opportunities to combine multiple sensor data sources using IoT technologies for better utilization of raw material in production lines. A common belief that data is readily available (the big data phenomenon), is oftentimes challenged by the need to effectively acquire quality data under severe constraints. In this paper we propose a design methodology, using active learning to enhance learning capabilities, for building a model of production outcome using a constrained amount of raw material training data. The proposed methodology extends existing active learning methods to effectively solve regression-based learning problems and may serve settings where data acquisition requires excessive resources in the physical world. We further suggest a set of qualitative measures to analyze learners performance. The proposed methodology is demonstrated using an actual application in the milk industry, where milk is gathered from multiple small milk farms and brought to a dairy production plant to be processed into cottage cheese.

Consider the problem where a statistician in a two-node system receives rate-limited information from a transmitter about marginal observations of a memoryless process generated from two possible distributions. Using its own observations, this receiver is required to first identify the legitimacy of its sender by declaring the joint distribution of the process, and then depending on such authentication, it generates adequate reconstruction of the observations, satisfying an average per-letter distortion. The performance of this setup is investigated through the corresponding rate-error-distortion region, describing the tradeoff between: the communication rate, the error exponent induced by the detection, and the distortion incurred by the source reconstruction. In the special case of testing against independence, where the alternative hypothesis implies that the sources are independent, the optimal rate-error-distortion region is characterized. An application example to binary symmetric sources is given subsequently and the explicit expression for the rate-error-distortion region is provided as well. The case of “general hypotheses” is also investigated. A new achievable rate-error-distortion region is derived based on the use of non-asymptotic binning, improving the quality of communicated descriptions. Further improvement of performance in the general case is shown to be possible when the requirement of source reconstruction is relaxed, which stands in contrast to the case of general hypotheses.

The problem of collaborative distributed hypothesis testing is investigated. In this setting, a binary decision is required about the joint distribution of two arbitrary dependent memoryless processes that are sampled at different physical locations (nodes) in the system. Interactive rate-limited communication is allowed between these nodes. Defining two types of error events, the error exponent for an error of the second type is investigated, under a prescribed probability of error of the first type. A general achievable error exponent, as a function of the total available communication resources, is proposed, for the case of two general hypotheses. The special case of testing against independence is revisited for which it is shown that optimality can be attained, as a special case of the general achievable exponent, provided the constraint over the error probability of the first type goes to zero.

A distributed hypothesis testing (HT) problem is considered, comprising two nodes and a unidirectional communication link. The receiving node is required to make a decision as to the probability distribution in effect. A binning process is used in order to minimize the probability of error, resulting in a new achievable error-exponent. A sub-class of HT problems with general hypotheses is defined, which contains many interesting and relevant problems. The advantage of the binning strategy in comparison to the non-binning approach is demonstrated by means of a binary symmetric example.

“Layered” rate-splitting based transmission strategies are investigated for the uplink of cellular communication systems employing clustered cooperative processing. Accordingly, partial decoding of some received out-of-cluster “layers” is employed, while undecoded “layers” are treated as noise. A two-dimensional Wyner-type system model is considered, by which only adjacent cell interference is present and characterized by a single parameter α ∊ (0, 1]. Focusing on the average throughput per cell, the setting is shown to be equivalent to a certain multiple-input multiple-output (MIMO) multiple access channel (MAC). An achievable average throughput is then obtained by efficiently solving an appropriately formalized Complementary Geometric Programming (CGP) problem. Singnificant performance enhancement is demonstrated compared to non-cooperative single-cell processing, as well as to “naive” cooperation, where out-of-cluster interference is treated as noise.

New challenges are arising in the design of computer systems with the emergence of new nanometer-scale devices and sophisticated fabrication techniques. Unfortunately, the yield, reliability, and drive characteristics of these new deep-submicron and nano-scale devices are different from the corresponding characteristics of conventional CMOS devices. It is expected that future circuit technologies will have substantially higher defect densities and dynamic fault rates. There is no consensus yet on which technology will be selected and which of the traditional logic designs has an advantage for fault tolerant nano-computing. In this work, we compare the robustness of several fault-tolerant approaches applied to lookup table design and random logic design for a wide range of fault rates. Implementing fault tolerance in a circuit using TMR and Hamming and Hsiao error correcting codes with a lookup table design style gives better fault coverage compared with a random gate design style. TMR is the best fault-tolerance technique when implemented using the lookup table design. However, TMR was the worst technique for fault rates greater than 0.5% when implemented using random logic design and no gate level is fault free.