In this paper, promising technologies and a network architecture are presented for future optical packet switched networks. The overall network concept is presented and the major choices are highlighted and compared with alternative solutions. Both long and shorter term approaches are considered, as well as both the wide-area network and multiple-area networks parts of the network. The results presented in this paper were developed in the frame of the research project DAVID (Data And Voice Integration over DWDM) project, funded by the European Commission through the IST-framework.

This paper presents a global methodology and optimization options for dimensioning the WDM optical layer in future transport networks. Several optimization processes are discussed and compared with results on the same study case, the European Optical Network. In particular, the results show the significant benefits of wavelength conversion and the advantages of "least number of hops" path routing among the various path routing strategies for wavelength channels. The connection rerouting optimization process, which requires a more algorithmic approach, is described along with the different criteria used to choose the optimized parameters (load on the link, fiber utilization ratio, etc.). The results on the European Optical Network case study illustrate that a global point of view should be adopted when optimizing these parameters as some processes can lead to worse dimensioning results.

The objective of this paper is to give an overview of the different studies we have performed at the research level regarding the design and implementation of a photonic wavelength division multiplexing (WDM) layer providing transparent transport services to client layers (SONET/SDH, ATM, etc.). Such a network requires a number of enabling factors to be assessed in order to become a reality. Among these factors are the availability of high-capacity WDM transmission systems and efficient optical routing nodes based on mature technology, the design of robust networks optimizing the utilization of resources, and the development of a management system in accordance with presently applied standards for transport networks. We review our achievements in these different fields.

This paper describes the work carried out in the RACE Project R2039 ATMOS (asynchronous transfer mode optical switching). The project is briefly illustrated, together with its main goal: to develop and assess concepts and technology suitable for optical fast packet switching. The project's technical approach consisted in the exploitation of the space and wavelength domains for fast routing and buffering: The major achievements are then reported. Four different switch architecture concepts have been proposed, investigated and developed, all based on a high speed optical routing matrix electrically controlled at lower speed. The basic optical key components and subsystems (wavelength converters, space switches and optical buffers) are described in detail, with the outstanding results obtained and the corresponding projected performance. In particular, system demonstration of wavelength conversion at 10 and 20 Gb/s has been realized, to show the usefulness of the ATMOS technology both to implement optimized high performance optical packet-switching fabrics as well as transparent optical circuit-routing nodes. Four rack-mounted, reduced size demonstrators of basic switching matrices have been designed and implemented scalable to real system sizes. The obtained good results in terms of bit error rate and hardware integration are reported, showing that ATM switches are feasible with state of-the-art optical technology.

A system concept based on a multipath self-routing switching principle and on an internal transfer mode using multislot cells is introduced. With the utilization of a shared buffer memory structure, this concept allows for a single-chip realization of the switching elements and fulfils important system requirements like fault tolerance, independence of the switch core from external data formats and traffic characteristics, and modular extendibility from small to very large systems. An example implementation of the concept with the resulting functional partitioning in boards and chips is given. Performance study results, as a basis for dimensioning, are also presented. The most important design aspects and a possible tool chain exploiting a hardware description language, logic simulator, and logic compiler are highlighted.>