Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-/spl mu/m CMOS technology show high correlation with the measurement data.

The design of on-chip ESD protection has become increasingly difficult and critical because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environments. A complex ESD protection network in an SoC can cause the degradation of circuit performance during normal operation. The loss introduced by ESD stress and protection networks is defined as ESD noise. In this paper, we present the generation and characterization of three different types of noise induced by ESD. The effect of ESD protection networks on sensitive circuits is investigated with a test chip processed in a 0.18 /spl mu/m CMOS technology. Experimental results suggest appropriate optimization of a tradeoff between ESD robustness and power supply coupling. It is important to note that, for mixed-signal design, the performance of a sensitive circuit is highly dependent on the ESD noise generated in the vicinity of the sensitive circuit, as well as circuit design techniques.