LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS addition/subtraction computation has made the large word-length LNS arithmetic implementation impractical. In this research, we proposed a hybrid floating-point (FLP)/LNS processor that can utilize the FLP multiplication-addition-fused (MAF) unit and the FLP division unit for implementing the computation of LNS addition/subtraction. With unified representation format in FLP and LNS numbers, this hybrid processor is versatile because it can execute the FLP-to-LNS and LNS-to-FLP conversions easily, without any extra hardware cost, in addition to the FLP multiplication-addition/subtraction, FLP division, and LNS addition/subtraction instructions. It is cost-effective because the FLP hardware is shared by the LNS unit. A 32-bit hybrid FLP/LNS processor is implemented on the Xilinx Virtex II multimedia FF896 development board. From the synthesis results, the hardware of the 32-bit hybrid processor is at most three times that of a 32-bit pure FLP processor. Our proposed hybrid FLP/LNS approach has made the design of very large word-length LNS arithmetic processors become practical.

This paper presents an efficient additive normalization method for exponential computation. Same as a previous additive normalization method, this new method can allow the values of the normalization factors in the normalization method be obtained directly from the remaining terms without any computation. Furthermore, the convergence rate of this method is also exponential. Instead of generating a group of logarithmic terms in each normalization stage, only one logarithmic term with large radix is generated and used as the normalization factor. This technique facilitates the computation of the partial result term in each normalization stage. The computation can then be implemented efficiently as a simple multiplication-and-add operation. Thorough simulations on the 24-bit exponential unit have verified that our proposed method is correct. From the synthesis results, the hardware cost and the delay of the proposed 53-bit exponential unit are only one-fourth and two-thirds of those of the 53-bit exponential unit in the previous design, respectively. We conclude that our proposed additive normalization method can significantly improve the performance of the exponential computation.

Pipelined computation of very large word-length LNS addition/subtraction requires a significant amount of hardware and long pipeline latency. We propose a base-e exponential algorithm to simplify the exponential computation and to replace half of the pipeline stages by multiplication-and-accumulate operations. By using this approach, the circuit cost of the previously proposed 64 bit pipelined LNS addition/subtraction unit can be reduced by more than fifty percent. We also developed signed-digit (SD) algorithms to further enhance the performance of the LNS computation. From our analysis, the throughput of the 64 bit LNS unit can be increased by a factor of 4.62, and the pipeline latency can be reduced by a factor of seven. Furthermore, this SD approach can still save more than 50% of the table size and 27.6% of the circuit of the previously proposed LNS unit. The proposed approaches and algorithms have been verified by comprehensive simulations on the designed 32 bit SD hardware-reduced LNS unit. We have concluded that the proposed approaches can significantly improve the performance of very large word-length LNS addition/subtraction computation.

Conventional additive normalization methods suffer from its linear convergence rate. We propose a new additive normalization method for the computation of exponential function. This new method can allow the values of the normalization factors be obtained directly from the remaining terms without any computation. Furthermore, the number of the normalization factors that are obtained in each normalization stage is twice that obtained from its previous stage. As a result, the convergence rate of our method is exponential. These two advantages of our new method can significantly enhance the speed and reduce the hardware cost of the additive normalization method. Based on our proposed additive normalization method, we have designed the architectures of a 24-bit exponential unit and a 53-bit exponential unit. From the results of our thorough simulations on the 24-bit unit, we have verified that our proposed algorithm and our error analysis method are correct.

Signed digit (SD) addition is applied to the design of a new floating-point (FLP) multiplication-add fused (MAF) unit. This adoption, together with the proposed two-step normalization method, can reduce the three-word-length addition that is required in the conventional FLP MAF unit to two-word-length addition. Furthermore, sign reversion of the intermediate mantissa that requires three-word-length carry propagation in the conventional MAF unit is replaced by only single-word sign detection. These two improvements can enhance the speed and cost of the MAF unit significantly. With the use of the SD addition, the circuit of the unit can be designed in a more regular and simple manner, which is a property that is desired in VLSI design. The proposed FLP MAF unit has been designed and simulated by using Verilog hardware description language. The functions of the designed unit are verified to be correct.

A novel pipelined method is proposed to compute the addition/subtraction in very large word-length logarithmic number system (LNS) arithmetic. Digit-parallel additive-normalization and digit on-line multiplicative-normalization methods are adopted to compute the exponential and logarithmic functions, respectively, in LNS addition/subtraction. These two methods can both be implemented in a pipelined and regular architecture. The size of the required lookup tables is now proportional to a third-order polynomial function, instead of an exponential function, of the word length. The total size of the tables in a 32-bit LNS unit is estimated to be less than 53.5 kbits and the total size of the table's in a 64-bit LNS unit will be less than 471 kbits. Furthermore, the hardware cost of the other circuits in the proposed LNS unit is only proportional to the square of the word length. This study also develops a simple leading-zero-bits prediction technique that can significantly enhance the precision in LNS addition/subtraction computation. When compared to floating-point arithmetic design, our approach still suffers from large hardware cost and pipeline latency. However, the proposed approach has provided a theoretical advancement in the development of very large word-length LNS arithmetic.

Logarithmic number system (LNS) has the advantages of regular data flow high speed, and high precision. However, the development of LNS arithmetic is hindered by the large size of the lookup tables used in LNS addition/subtraction, since the size is exponentially proportional to the word length of the operands. To overcome this large-table problem, LNS addition/subtraction is proposed to be computed in a pipelined manner. The computation includes an exponential stage and a logarithmic stage. The exponential stage is implemented by using digit-parallel additive normalization and the logarithmic stage is implemented by using digit on-line multiplicative normalization. It has been computed that the size of the lookup tables used in a 33-bit LNS unit is about 0.543 Mbits, which is very small. The hardware cost of the other circuits in this LNS unit is only linearly proportional to the word length of the operands. We conclude that the proposed method makes large word-length LNS arithmetic possible.

The use of vision sensors to study object deformation is discussed. The vision sensor is used to identify the deformation characteristic and estimate the deformation of flexible beams. First, a nonlinear equation describing the deformation of the beam is given. Then, cubic spline functions are used to approximate the contour of the deformed beam after the beam is detected by the vision sensor. Using the cubic spline approximation and Maclaurin's series expansion, a procedure for determining the deformation characteristic is formulated. To estimate the deformation of the beam, a numerical differential method for solving the nonlinear equation is used. The error of this numerical method can be controlled with the aid of the vision sensor. Experimental results are given to verify that the proposed methods are effective.>

Strategies for automatic assembly of deformable objects are presented. A flexible beam mating with a rigid hole is taken as the target of investigation. The deflection behavior of a deformable beam is studied. The geometric and force conditions for successful assembly of rigid parts are reviewed. Based on these conditions, strategies for assembling deformable beams are proposed. The strategies are defined by the motion trajectory of the tool which handles the beam. It is found that when the clearance between the beam and the hole is loose, the desired trajectory should be the same as the curve formed by the deformed beam. When the clearance is tight, the position and orientation of the tool should be adjusted, following the involute of the deformed beam curve.>