Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

Adelmo Ortiz-Conde

dblp:48/3900 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 2002
0000-0001-5073-5396ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Hardware reliability and fault tolerance · 25% Electronic design automation · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.012002
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation
circuit simulation		 0.012002
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Integrated circuit design › analog and mixed-signal circuits
device modeling		 0.012002
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Hardware reliability and fault tolerance › design for reliability
electrostatic discharge protection		 0.012002
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002

Methods — techniques the papers use, named apart from their topics

SPICE simulation · 0.0MOSFET modeling · 0.0
YearPublicationVenuePosition
2002 Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications
abstract
Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a comprehensive computer-aided design tool for ESD applications. Specifically, the authors develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. The key components relevant to ESD in the MOS model are studied and the implementation procedure is discussed. Experimental data measured from the human body model tester are included in support of the model.
Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5