An all-in-one anomaly-detection processor for an extensive range of industrial applications is presented. This processor uniquely integrates A/D converters as a multiple-sensor interface, a generator of pseudo images and a DNN accelerator for image recognition on a single 7nm CMOS chip. The chip can process not only images but also any sensor signals with enhanced sensor-fusion capability. It operates with only 150mW power at 100MHz under a supply voltage of 0.75V, including the 16-channel A/D converters. The effectiveness of this single-chip anomaly-detection processor is proved with two actual industrial applications. To the best of the authors’ knowledge, this is the first integration of digital AI and high-performance A/D converters with a FinFET CMOS technology.

Edge computing provides new possibilities for Deep Neural Network (DNN) applications, but the constrained resources of edge devices pose limitations to real-time inference execution. Much effort has been devoted to DNN pruning. However, conventional pruning methods often cause degradation of the detection accuracy. In this work, we try to answer how pruning can be performed without paying the price of performance loss. Conventional filter-level pruning methods remove filters demanded as less important. The drawback is that the pruned information is lost, and the detection accuracy deteriorates. To address this issue, we propose a new filter-level pruning method to enable real-time inference execution of DNNs on edge devices, while minimizing the detection accuracy drop. Our proposed pruning method analyzes layers' properties to assign to each layer a different pruning ratio, proportional to how much pruning the layer will impact the overall detection accuracy. Inside each layer, a percentage of filters that produce similar information is removed. Experimental results show that our pruning method yields accurate and compact DNNs, with minimal loss in performance. For a custom object detection network, based on the popular YOLO v3, we reduce the network filters by 60% and floating-point operations (FLOPs) by 80%. Experimental evaluations on Jetson Nano demonstrate that our proposed pruning method increases the inference speed by 16%. Compared to the original heavy network, the pruned network achieves a comparable accuracy, but with significantly lower memory usage and computational cost, making the solution suitable for real-time inference.

A new control scheme for eliminating garbage collection during high-speed analysis of big-graph data stored in NAND flash memory is proposed and evaluated. During big-graph analysis, intermediate results of the analysis are stored in NAND flash memory and updated repeatedly. Under a conventional control scheme, excessive data copying, called “garbage collection,” occurs because overwriting data to NAND flash memory is prohibited. Such excessive data copying degrades performance of big-graph analysis. In contrast, under the proposed control scheme, the controller of NAND flash memory writes the intermediate results, which are updated at the same time, to the same block of NAND flash memory, and the excessive data copying is eliminated completely because all the data in the block can be erased at the same time before the intermediate results are updated. As a result, the proposed scheme shortens analysis time by 88 percent and increases analysis speed for big graphs 8.7 times. The proposed scheme can be applied to three-dimensional NAND flash memory and increases analysis speed 9.5 times. Also, the proposed scheme can be applied to an emerging high-density memory such as three-dimensional vertical chain-cell phase-change memory. These results show that the proposed control scheme enables high-speed analysis of big graphs.

A new control scheme for eliminating garbage collection during high-speed analysis of big-graph data stored in NAND flash memory is proposed and evaluated. During big-graph analysis, intermediate results of the analysis stored in NAND flash memory are updated repeatedly. When a conventional control scheme is applied, excessive data copying, called “garbage collection,” occurs because overwriting data to NAND flash memory is prohibited. Such excessive data copying degrades the performance of big-graph analysis. When the proposed control scheme is applied, the controller of NAND flash memory writes the intermediate results which are updated at the same time to the same block of NAND flash memory, and the excessive data copying is eliminated completely because all the data in the block can be erased at the same time before the intermediate results are updated. As a result, the proposed control scheme shortens analysis time by 88% and increases analysis speed for big graphs 8.7 times. These results show that the proposed control scheme enables high-speed analysis of big graphs.

We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40 % and latency by 38 % compared to those of standby mode. An SDRAM controller was developed based on this scheme and 0.18-um CMOS technology. The area of the controller is 0.28mm 2 and its operating current is 2.5mA at 1.8V and 100 MHz. Keywords: SDRAM controller, standby mode, active-standby mode Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.