This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time program trace compressor, named trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the trace compressor, named the online mode, or exclusively as the trace compressor, named the bypass mode. The RTL implementation of a 4 KB trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address trace as well.

This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (aHb multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13-m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%-96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The compression algorithm must be simple for hardware implementation; a common method is to store only the difference between the previous value and the current one. Such differential compression has trouble with the circular buffer that is needed for recording continuous traces. Previous solutions are complex and waste memory. By a transformation that expresses differential compression in reverse form, we derive a new solution that is simpler than previous methods and does not waste memory. Our algorithm is based on an innovative reverse-encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a real-time on-chip advanced high-performance bus tracer and has been embedded in a 3-D graphics system-on-a-chip as an application example. The bus tracer costs only 44 K gates and runs at 500 MHz in TSMC 0.13-¿m technology. Experiments have shown that our bus tracer achieves 100% circular-buffer utilization and captures 4.86 times trace depths as compared with a conventional industrial approach.

The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus, makes it difficult to reconstruct the trace from the incomplete information stored in the circular buffer. This paper proposes an efficient compression algorithm which is capable of compressing both pre-T and post-T traces. The algorithm is based on an innovative reverse encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a realtime on-chip AHB bus tracer and has been embedded in a 3D graphics SoC as an application example. The bus tracer costs only 44K gates and runs at 500MHz on 0.13um technology. Experiments have shown that this bus tracer achieves 100% circular buffer utilization and captures 1.2x and 4.86x trace depths than state-of-the-art related work and conventional industrial approaches, respectively.

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

This demonstration shows how we can enable the SoC debugging and performance evaluation with the reverse-encoding-based on-chip AHB bus tracer. By embedding this bus tracer to a SoC, designers can observe and debug the SoC internal states easily. The bus tracer supports both Pre-Triggering (Pre-T) trace and Post- Triggering (Post-T) trace at high compression ratio. For Post-T trace, designs can monitor signals for a known period at different abstraction level. It is very helpful for designs to realize the top view and detail view of the system for performance evaluation and debugging. Pre-T trace captures signals before an event occurs. It is very helpful for system error diagnosis since the errors are unexpected.

The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. This paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the OCB. The verification approach is based on the Processor External Interrupt Verification Tool (PEVT) whose simulation environment is direct-connected memory. In this paper, we implement the PEVT-SoC and successfully verify two SoC platforms, one academic microprocessor and one public domain microprocessor. An interesting bug appears that is impossible to be discovered in the memory bus and not easy to be identified on the OCB. The result shows that the PEVT-SoC effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. With little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.

Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called processor exception verification tool (PEVT), to verify the external interrupt behaviors of microprocessors, including individual, multiple, and nested interrupts. An architecture description language extension, called Exception Description Language (EXPDL), is developed for the designer to capture the external interrupt behaviors for the microprocessor under verification. PEVT is responsible for generating the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of the ARM7 microprocessor core and a public domain scalable processor architecture (SPARC) microprocessor core. The ARM7 has had a system-on-a-chip test chip and software porting including multimedia applications (MP3/JPEG/ ...) and a real time operating system muC-OSII. PEVT successfully identified several sophisticated remaining bugs with 527 lines of EXPDL description and took only 4 204 961 cycles of register transfer language simulation with execution time of 4.5 h in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 98 cycles per case on the average, which identify potential bugs with much less simulation cycles at the early verification stage, compared with traditional manual-based approaches.

A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock frequency comparing to ARM7, even the performance is 67% better in narrow width memory at the same clock frequency. The ARM7 software is also compatible.

Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This paper proposes a CAD tool, called PEVT, to verify the external interrupt behaviors of microprocessors. An architecture description language extension, called EXPDL, is developed for the designer to capture the external interrupt behaviors for the microprocessor. PEVT is responsible to generate the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of ARM7 microprocessor core, which has had a SoC test chip and software porting including MP3 decoder and uC-OSII. PEVT successfully identified several sophisticated remaining bugs with only less than 88,000 cycles of RTL simulation with execution time of 424 seconds in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 21 cycles per case on the average, which identify potential bugs with much less simulation cycles, compared with traditional regression tests which consume huge amount of simulation cycles.