The hybrid model of CNN(Convolution Neural Networks) and Transformer is a popular method in segmenting kidney images, but most existing hybrid models directly fused local features from CNN with global features from Transformer, ignoring the issue of semantic gaps between distinct features. Furthermore, feature fusion is typically performed solely at the feature level, without considering alignment at the mask (prediction map) level. To address these limitations, we propose a novel segmentation method called Dual-level Combination of CNN and Transformers Network (DCCTNet). Specifically, we select similar features from both CNN and Transformer to reduce semantic gaps at the feature level. Additionally, we further utilize the global information of the Transformers by reducing the difference between the prediction maps in the coding stage at the mask level. We evaluate DCCTNet on the KiTS19 dataset, achieving $97.3 \%$ dice score for kidneys segmentation and $81.2 \%$ dice score for kidney tumors segmentation, respectively. https://github.com/hou-bz/DCCTNet.

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device.This paper presents a network-flow baaed partitioning algorithm for dynamically reconfigurable FP-GAS based on the architecture in [2].Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

Presents an optimal algorithm to solve the schedule compression problem, which is an open problem proposed by S. Trimberger (1998) for time-multiplexed FPGA partitioning. Time-multiplexed FPGAs have the potential to dramatically improve logic density by time-sharing logic. Schedule compression is an important step in partitioning for time-multiplexed FPGAs and can greatly influence the quality of the partitioning solution. We exactly solve the schedule compression problem by converting it to a constrained min-max path problem. We further extend our algorithm to minimize the communication cost during schedule compression. Experiments show that our optimal algorithm outperforms the existing heuristics and runs very efficiently.

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new FPGA architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. The feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementations. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g. Actel's ES6500 FPGA family).

Time-multiplexed FPGAs have the potential to dramatically improve logic density by time-sharing logic, and have become an active research for reconfigurable computing. The partitioning problem for time-multiplexed FPGAs is different from the traditional partitioning problem in that the nodes have precedence constraints among them, and the widely used iterative improvement partitioning methods such as K&L, FM [14,15] are no longer applicable. All previous approaches [1,2,3] used list scheduling heuristics. In this paper, we present a network flow based algorithm for multi-way precedence constrained partitioning, which can handle the precedence constraints while minimizing the netcut size. The experimental results on the MCNC benchmark circuits show that our algorithm out-performs list scheduling by a big margin, with an average improvement of over 50% for bipartitioning and 20% for multi-way partitioning. 1 Introduction One of the major benefits provided by FPGAs is the ability of ru...

Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

Network flow is an excellent approach to finding min-cuts because of the celebrated max-flow min-cut theorem. For a long time, however, it was perceived as computationally expensive and deemed impractical for circuit partitioning. Recently, the algorithm FBB successfully applied network flow to two-way balanced partitioning. It for the first time demonstrated that network flow was a viable approach to circuit partitioning. In this paper, we present FBB-MW, which is an extension of FBB, to solve the problem of multiway partitioning with area and pin constraints. Experimental results show that FBB-MW outperforms previous approaches for multiple field programmable gate array partitioning. In particular, although FBB-MW does not employ logic replication and logic resynthesis, it still outperforms some other algorithms, which allow replication and resynthesis for optimization.

A scalable web server architecture is key to enabling WWW sites to handle the ever increasing traffic loads. There is empirical evidence that, for the current generation of web server applications, multiprocessor platforms do not provide the needed scalability to handle large traffic volumes. This is primarily due to the fact that current TCP/IP implementations are single-threaded which severely limits the multiprocessor speedup for HTTP server applications. Therefore a distributed architecture consisting of independent servers sharing the load is more appropriate for implementing a scalable web server. Most current distributed server platforms typically use some form of Round-Robin or weighted Round-Robin implemented using the DNS server. This approach for distributing the load requires each HTTP server to handle requests for all the data stored at the site which implies that either each server must store its own copy of all the data available at the site or it must access the data from other HTTP servers or some dedicated back-end file or database servers thus generating significant back-end traffic. Neither of these options scale effectively because they lead to bottlenecks in the LAN or back-end servers or require significant additional resources. The "redirection-based" hierarchical server architecture eliminates bottlenecks in the server complex and allows for hardware to be added seamlessly to handle increases in load. In this approach, two levels of servers are used: redirection servers and normal HTTP servers. Data are partitioned according to their content and stored on different HTTP servers. Redirection servers are used to distribute the users' requests to the corresponding HTTP servers using the redirection mechanism supported by the HTTP protocol. This approach is completely transparent to the user, allows for intelligent distribution of load among servers, and achieves better caching efficiency compared with other load balancing schemes.

Network flow is an excellent approach to finding min-cuts because of the celebrated max-flow min-cut theorem.However, for a long time, it was perceived as computationally expensive and deemed impractical for circuit partitioning.Only until recently, FBB [l] successfully applied network flow to two-way balanced partitioning and for the first time demonstrated that network fow was a viable approach to circuit partitioning.In this paper, we present FBB-MW, which is an extension of FBB, to solve the problem of multi-way partitioning with area and pin constraints.Experimental results show that FBB-MW outperforms the FM-based MW-part program in the TAPIR package[lO].1. *This work was partially

This paper proposes an effective next view planning strategy for the object recognition and localization task in a model-based robot vision system. A set of rules are designed to automatically predict new features and calculate the next optimal placement of the sensor so that the most useful information can be gathered from multi-views. A state vector (i,r,t) is defined to describe the current state of the vision system and each possible state corresponds to a subset of rules to deal with it. The recognition and location task can be described as a process of rule calling and state conversions. The most suitable rule is selected at each step to try to acquire more useful information as soon as possible. Experiments are shown in the paper.>