Heterogeneous architectures with single-instruction set architecture (ISA) asymmetric cores can improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA heterogeneous core architectures. The basic idea is to collect multiple traces by running a workload on different homogeneous platforms, and to align these traces for offline analysis. For this, we propose a wavelet-based similarity metric, which captures both fine-grain and coarse-grain software phases across different traces. Then, we propose a scalable dynamic programming algorithm to optimize this metric to align the traces. Our experiments show that the runtime and energy values predicted by our offline methodology have good accuracy with respect to the real measurements from a prototype heterogeneous system.

Heterogeneous architectures with single-ISA asymmetric cores have the potential to improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA heterogeneous core architectures. The basic idea is to collect multiple traces by running a workload on different homogeneous platforms, and to align these traces for offline analysis. For this, we propose a wavelet-based similarity metric, which captures both fine-grain and coarse-grain software phases across different traces. Then, we propose a scalable dynamic programming algorithm to optimize this metric to align the traces. Our experiments show that the runtime and energy values predicted by our offline methodology have good accuracy with respect to the real measurements from a prototype heterogeneous system. The proposed methodology can enable design space exploration of single-ISA heterogeneous multi-core systems using traces from off-the-shelf homogeneous systems.

Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The effectiveness of heterogeneous multi-cores depends on how well a scheduler can map workloads onto the most appropriate core type. In general, small cores can achieve good performance if the workload inherently has high levels of ILP. On the other hand, big cores provide good performance if the workload exhibits high levels of MLP or requires the ILP to be extracted dynamically. This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance. PIE collects CPI stack, MLP and ILP profile information, and estimates performance if the workload were to run on a different core type. Dynamic PIE adjusts the scheduling at runtime and thereby exploits fine-grained time-varying execution behavior. We show that PIE requires limited hardware support and can improve system performance by an average of 5.5% over recent state-of-the-art scheduling proposals and by 8.7% over a sampling-based scheduling policy.

A key functionality in today's widely used interior gateway routing protocols such as OSPF and IS-IS involves the computation of a shortest path tree (SPT). In many existing commercial routers, the computation of an SPT is done from scratch following changes in the link states of the network. As there may coexist multiple SPTs in a network with a set of given link states, such recomputation of an entire SPT not only is inefficient but also causes frequent unnecessary changes in the topology of an existing SPT and creates routing instability. This paper presents a new dynamic SPT algorithm that makes use of the structure of the previously computed SPT. Our algorithm is derived by recasting the SPT problem into an optimization problem in a dual linear programming framework, which can also be interpreted using a ball-and-string model. In this model, the increase (or decrease) of an edge weight in the tree corresponds to the lengthening (or shortening) of a string. By stretching the strings until each node is attached to a tight string, the resulting topology of the model defines an (or multiple) SPT(s). By emulating the dynamics of the ball-and-string model, we can derive an efficient algorithm that propagates changes in distances to all affected nodes in a natural order and in a most economical way. Compared with existing results, our algorithm has the best-known performance in terms of computational complexity as well as minimum changes made to the topology of an SPT. Rigorous proofs for correctness of our algorithm and simulation results illustrating its complexity are also presented.

Future broadband networks may provide very high bandwidth on demand for certain applications e.g. downloading of a gigabyte file to a high-performance workstation. Motivated by such applications, we study the performance of TCP under the scenario where there is long network latency and rapidly changing bandwidth. We show that existing TCP cannot utilize the bandwidth effectively under such network dynamics. We propose a modification of TCP that would separate the flow control from the loss recovery mechanisms, allowing the efficient use of the available bandwidth over a network that has a high bandwidth-delay product and in which the bandwidth can vary by orders of magnitude over a short period of time. We present simulation results demonstrating the significant performance gain of our new approach.

The open shortest path first (OSPF) and IS-IS routing protocols widely used in today's Internet compute a shortest path tree (SPT) from each router to other routers in a routing area. Many existing commercial routers recompute an SPT from scratch following changes in the link states of the network. Such recomputation of an entire SPT is inefficient and may consume a considerable amount of CPU time. Moreover, as there may coexist multiple SPTs in a network with a set of given link states, recomputation from scratch causes frequent unnecessary changes in the topology of an existing SPT and may lead to routing instability. We present new dynamic SPT algorithms that make use of the structure of the previously computed SPT. Besides efficiency, our algorithm design objective is to achieve routing stability by making minimum changes to the topology of an existing SPT (while maintaining shortest path property) when some link states in the network have changed. We establish an algorithmic framework that allows us to characterize a variety of dynamic SPT algorithms including dynamic versions of the well-known Dijkstra, Bellman-Ford, D'Esopo-Pape algorithms, and to establish proofs of correctness for these algorithms in a unified way. The theoretical asymptotic complexity of our new dynamic algorithms matches the best known results in the literature.

Link-state protocols such as OSPF are the dominant routing technology in today's Internet. Despite their many advantages, these protocols require the flooding of new information across the entire routing area after changes in any link state (e.g., link failures). As the routing area grows or the frequency of link-state changes increases, the overhead (in terms of bandwidth and processing cost) of flooding becomes prohibitive. Furthermore, such flooding over a large area will cause temporary inconsistency of link states among many routers, potentially creating many transient routing loops that can last for a long time. This limits the scalability of the routing protocols to large routing areas. To overcome such problems, we present in this paper a novel algorithm that minimizes the amount of information distributed by link-state routing protocols. Upon a link failure, our algorithm will distribute the link-state changes to the minimum number of routers that are needed to ensure loop-free routing. Moreover, implementing our algorithm requires only a simple extension to any existing link-state protocol.

A key functionality in today's widely used interior gateway routing protocols such as OSPF and IS-IS involves the computation of a shortest path tree (SPT). In many existing commercial routers, the computation of an SPT is done from scratch following changes in the link states of the network. As there may coexist multiple SPTs in a network with a set of given link states, such recomputation of an entire SPT not only is inefficient but also causes frequent unnecessary changes in the topology of an existing SPT and creates routing instability. This paper presents a new dynamic SPT algorithm that makes use of the structure of the previously computed SPT. This algorithm is derived by recasting the SPT problem into an optimization problem in a dual linear programming framework, which can also be interpreted using a ball-and-string model. In this model, the increase (or decrease) of an edge weight in the tree corresponds to the lengthening (or shortening) of a string. By stretching the strings until each node is attached to a tight string, the resulting topology of the model defines an (or multiple) SPT(s). By emulating the dynamics of the ball-and-string model, we can derive an efficient algorithm that propagates changes in distances to all affected nodes in a natural order and in a most economical way. Compared with existing results, our algorithm has the best-known performance in terms of computational complexity as well as minimum changes made to the topology of an SPT. Rigorous proofs for correctness of our algorithm and simulation results illustrating its complexity are also presented.

We study a typical network environment where TCP traffic is generated from a source connected to a LAN (e.g. Ethernet) aggregated through an IP edge router to an access network (e.g. ATM, frame relay). Congestion at the edge router occurs when the bandwidth available in the access network cannot support the aggregated traffic generated from the LAN. This paper presents a novel approach to reduce router congestion and improve TCP performance. In particular, we propose new techniques that regulate TCP acknowledgments at the edge router without changing existing TCP implementations at the end systems. Our techniques minimize buffer requirement at network edges while maximizing the throughput. Analytical and simulation results are presented in the's paper to substantiate our claims.

The efficient support of data traffic over ATM networks requires congestion control, whose objectives include maximizing throughput, minimizing switch buffer requirement, and attaining a fair bandwidth allocation. With available bit rate (ABR) service in ATM, congestion control is achieved by requiring data sources to adjust their rates based on the feedback from the network. The difficulties in providing effective ABR service are caused by the burstiness of data traffic, the dynamic nature of the available bandwidth, as well as the feedback delay. Using a new design methodology described in our previous paper, we present here a congestion control algorithm that is provably stable and is optimal in the sense that it has the shortest possible transient response time. Moreover, our algorithm achieves fair bandwidth allocation among contending connections and maximizes network throughput. It also delivers good performance for switches that use a FIFO queuing discipline. Essentially, the algorithm implicitly measures the round-trip delay using resource enhancement cells, and establishes an observer (in the control theoretic sense) to control the flow of data in the network. Rigorous analysis as well as simulation results are presented to substantiate our claims.