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Yi Chen 0035

dblp:49/6574-35 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2026
0009-0004-8249-1567ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Segmentation and scene understanding · 33% Language models and text generation · 33% Efficient and distributed learning · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 87% GPUs and heterogeneous computing · 13%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Natural language and speech › Language models and text generation › prompting
automatic prompt generation
0.912025
AoP-SAM: Automation of Prompts for Efficient Segmentation · AAAI 2025
Machine learning › Efficient and distributed learning
inference efficiency
0.912025
AoP-SAM: Automation of Prompts for Efficient Segmentation · AAAI 2025
Computer vision › Segmentation and scene understanding
prompt-based segmentation
0.912025
AoP-SAM: Automation of Prompts for Efficient Segmentation · AAAI 2025
Cryptographic primitives and cryptanalysis
homomorphic encryption
0.712023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023
Cryptographic primitives and cryptanalysis › homomorphic encryption › fully homomorphic encryption
TFHE
0.712023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.712023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023
Hardware accelerators and domain-specific architectures › cryptographic accelerator
fully homomorphic encryption accelerator
0.712023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023
GPUs and heterogeneous computing
GPU computing
0.212023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping · MICRO 2023

Methods — techniques the papers use, named apart from their topics

programmable bootstrapping · 1.3ciphertext batching · 1.3test-time adaptive sampling · 0.9prompt engineering · 0.9
YearPublicationVenuePosition
2026 An End-to-End Diffusion Accelerator With Reconfigurable Hyper-Precision and Unified Non-Matrix Processing Engine
abstract
Diffusion models have emerged as state-of-the-art generative AI models but face significant computational challenges due to their iterative denoising process. While quantization techniques help reduce computation, conventional methods often degrade accuracy, and non-matrix operations remain a latency bottleneck. We propose Picasso, an end-to-end diffusion accelerator featuring the novel Hyper-Precision 8 (HYP8) data type that balances numerical precision and hardware efficiency by extending dynamic range while preserving resolution for near-zero values. Picasso integrates Hyper-Efficient Reconfigurable Arrays (HERA) for matrix operations and Unified Non-Matrix Processing Engines (UNPE) for normalization, softmax, and element-wise computations. Fabricated in a 28-nm CMOS process, Picasso achieves 9.83 TOPS with 4.96 TOPS/W energy efficiency, outperforming prior works by up to$26.8\times $in speed,$2.8\times $in energy efficiency, and$30.5\times $in area efficiency, while maintaining FP16-equivalent generation quality with reduced memory footprint.
Sungyeob Yoo, Seeyeon Kim, Geonwoo Ko, Seri Ham, Yi Chen 0035, Joo-Young Kim 0001
IEEE Trans. Circuits Syst. I Regul. Pap.5
2025 AoP-SAM: Automation of Prompts for Efficient Segmentation
abstract
The Segment Anything Model (SAM) is a powerful foundation model for image segmentation, showing robust zero-shot generalization through prompt engineering. However, relying on manual prompts is impractical for real-world applications, particularly in scenarios where rapid prompt provision and resource efficiency are crucial. In this paper, we propose the Automation of Prompts for SAM (AoP-SAM), a novel approach that learns to generate essential prompts in optimal locations automatically. AoP-SAM enhances SAM’s efficiency and usability by eliminating manual input, making it better suited for real-world tasks. Our approach employs a lightweight yet efficient Prompt Predictor model that detects key entities across images and identifies the optimal regions for placing prompt candidates. This method leverages SAM’s image embeddings, preserving its zero-shot generalization capabilities without requiring fine-tuning. Additionally, we introduce a test-time instance-level Adaptive Sampling and Filtering mechanism that generates prompts in a coarse-to-fine manner. This notably enhances both prompt and mask generation efficiency by reducing computational overhead and minimizing redundant mask refinements. Evaluations of three datasets demonstrate that AoP-SAM substantially improves both prompt generation efficiency and mask generation accuracy, making SAM more effective for automated segmentation tasks.
Yi Chen 0035, Muyoung Son, Chuanbo Hua, Joo-Young Kim 0001
AAAI1
2024 Picasso: An Area/Energy-Efficient End-to-End Diffusion Accelerator with Hyper-Precision Data Type
abstract
This work presents Picasso, an end-to-end diffusion accelerator designed for enhancing the efficiency of diffusion-based machine learning models used in applications such as image and video generation, and inpainting. Picasso introduces a novel hyper-precision 8 (HYP8) data type and a reconfigurable architecture designed to significantly enhance hardware efficiency, providing an extended dynamic range without sacrificing accuracy. It also features a unified engine that streamlines the processing of all non-matrix operations and employs sub-block pipeline scheduling to reduce overall latency. Fabricated in 28nm CMOS technology, this accelerator achieves an energy efficiency of 4.96 TOPS/W and a peak performance of 9.83 TOPS. Compared to previous works, Picasso demonstrates speedups ranging from 8.4× to 26.8× while also improving energy and area efficiency by 1.1× to 2.8× and 3.6× to 30.5×, respectively.
Sungyeob Yoo, Geonwoo Ko, Seri Ham, Seeyeon Kim, Yi Chen 0035, Joo-Young Kim 0001
HCS5
2023 Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping
abstract
Homomorphic encryption (HE) is a type of cryptography that allows computations to be performed on encrypted data. The technique relies on learning with errors problem, where data is hidden under noise for security. To avoid excessive noise, bootstrapping is used to reset the noise level in the ciphertext, but it requires a large key and is computationally expensive. The fully homomorphic encryption over the torus (TFHE) scheme offers a faster and programmable bootstrapping (PBS) algorithm, which is crucial for many privacy-focused applications. Nonetheless, the current TFHE scheme does not support ciphertext packing, resulting in low-throughput performance. To the best of our knowledge, this is the first work that thoroughly analyzes TFHE bootstrapping, identifies the TFHE acceleration bottleneck in GPUs, and proposes a hardware TFHE accelerator to solve the bottleneck.
Adiwena Putra, Prasetiyo, Yi Chen 0035, John Kim 0001, Joo-Young Kim 0001
MICRO3