Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters.

Modern devices often include several embedded instruments, such as BIST interfaces, sensors, calibration facilities. New standards, such as IEEE Std 1687, provide vehicles to access these instruments. In approaches based on reconfigurable scan networks (RSNs), instruments are coupled with scan registers, connected into chains and interleaved with reconfigurable modules. Such modules embed reconfigurable multiplexers that permit a selective access to different parts of the chain. A similar scenario is also supported by IEEE Std 1149.1-2013. The test of permanent faults affecting an RSN requires to shift test vectors throughout a certain number of network configurations. This paper presents some methodologies to select the list of configurations that perform the complete test of the reconfigurable modules of the RSN. In particular, one method is presented that, by construction, can be proved to be able to apply the test in the minimum amount of clock cycles. Other methods are sub-optimal in terms of test application time (TAT), but scale well on large circuits. In order to provide a comparison between the proposed methods, experimental results on some benchmark RSNs are provided.

Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded monitoring instruments detect faults to the time when the fault manager localizes the faults. In this article, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected faults are automatically included in the scan path, and a fault detection and localization module in hardware that detects the configuration of the network after self-reconfiguration and extracts the error codes reported by the fault monitoring instruments. To enable self-reconfiguration, we propose a modified segment insertion bit (SIB) compliant to IEEE 1687. We provide time analyses on fault detection and fault localization for single and multiple faults, and suggest how the self-reconfiguring IEEE 1687 network should be designed such that time for fault detection and fault localization is kept low and deterministic. We show that compared with previous schemes, our proposed network significantly reduces the fault localization time. For validation, we implemented a number of self-reconfiguring networks as well as their corresponding fault detection and localization modules in hardware, and performed post-layout simulations. We show that for large number of instruments, implementing the fault detection and localization module in hardware results in less area compared with the corresponding software-based implementation. Another benefit of the hardware implementation over its software counterpart is that to achieve the same fault detection and localization time, the hardware module can be clocked at a lower frequency than the core on which the corresponding software implementation would run.

The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, diagnosis, calibration, etc.), by using configuration modules which act as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. The resulting networks might be affected by defects preventing their correct operation. This necessitates the availability of solutions which allow not only to test against defects, but also to identify the location of possible faults via diagnosis. This paper for the first time addresses the problem of the diagnosis of IEEE 1687 networks. Experimental results gathered on a set of benchmark networks show the feasibility of the solution and provide a first idea about the length of the required input stimuli.

Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. In this paper, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected errors are automatically included in the scan path. To enable self-reconfiguration, we propose a modified segment insertion bit (SIB) compliant to IEEE 1687. We provide time analyses on error detection and fault localization for single and multiple faults, and we suggest how the self-reconfiguring IEEE 1687 network should be designed such that time for error detection and fault localization is kept low and deterministic. For validation, we implemented and performed post-layout simulations for one self-reconfiguring network. We show that compared to previous schemes, our proposed network significantly reduces the fault localization time.

The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli.

The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community.

IEEE 1687 enables flexible access to on-chip instruments via dynamically reconfigurable networks. Reconfiguration allows reducing instrument access time by keeping only those instruments on the scan-path which are required for each access. To perform reconfiguration and execute commands described in instrument access procedures, scan vectors are generated in a process called retargeting. These vectors are then applied through a number of capture-shift-update (CSU) operations. Generating the optimal set of vectors w.r.t. application time is modeled as an Integer Linear Optimization Problem, which is an NP-hard problem. In the modeling, an IEEE 1687 network is represented as a sequential problem unrolled over a number of time frames, each frame corresponding to a CSU operation. A key challenge is to find the number of required CSU operations, which should be sufficiently high so that the optimal solution is included in the search space but kept as low as possible to keep the model less complex and thus suitable for large IEEE 1687 networks. In this work, we propose a method to compute an upper-bound on the number of required CSU operations. Through experiments, we show that our method results in a tight upper-bound, is applicable to a large variety of IEEE 1687 network designs, and is able to handle large designs.

Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach.

IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the runtime for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors.

IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on fault injection and fault handling. Our MPSoC demonstrator consists of (1) an MPSoC model with a set of components (devices) each equipped with fault detection features, so called instruments, (2) an Instrument Access Infrastructure (IAI) based on IEEE P1687 that connects the instruments, (3) a Fault Indication and Propagation Infrastructure (FIPI) that propagates fault indications to system-level, (4) a Resource Manager (RM) to schedule jobs based on fault statuses, (5) an Instrument Manager (IM) connecting the IAI and the RM, and (6) a Fault Injection Manager (FIM) that inserts faults. The main goal of the demonstrator is to enable experimentation on different fault handling solutions. The novelty in this particular demonstrator is that it uses the existing test features, i.e. IEEE P1687 infrastructure, to assist fault handling. The demonstrator is implemented and a case study is performed.

It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks.

While the advancement in semiconductor technologies enables manufacturing of highly advanced and complex integrated circuits, there is an increasing need of embedded (on-chip) instruments for test, debug, diagnosis, configuration, monitoring, etc. A key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers low-cost, non-intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. This paper discusses the need of embedded instrumentation, the shortcomings of IEEE 1149.1 as well as features and challenges of IEEE P1687.

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.

In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC'02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

The IEEE P1687 (IJTAG) standard proposal aims at standardizing the access to embedded test and debug logic (instruments) via the JTAG TAP. P1687 specifies a component called Segment Insertion Bit (SIB) which makes it possible to construct a multitude of alternative P1687 instrument access networks for a given set of instruments. Finding the best access network with respect to instrument access time and the number of SIBs is a time-consuming task in the absence of EDA support. This paper is the first to describe a P1687 design automation tool which constructs and optimizes P1687 networks. Our EDA tool, called PACT, considers the concurrent and sequential access schedule types, and is demonstrated in experiments on industrial SOCs, reporting total access time and average access time.

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.