Demo Data from SIGIR 2026 / reviewers in the wild / expert
Chandra R. Vora
dblp:51/5150
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 87% Parallel and multicore computing · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory access
parallel memory access |
0.0 | 1 | 1982 | The Prime Memory System for Array Access · IEEE Trans. Computers 1982 |
Memory systems › memory architecture
prime memory system |
0.0 | 1 | 1982 | The Prime Memory System for Array Access · IEEE Trans. Computers 1982 |
Parallel and multicore computing
array processor |
0.0 | 1 | 1982 | The Prime Memory System for Array Access · IEEE Trans. Computers 1982 |
Methods — techniques the papers use, named apart from their topics
indexing hardware · 0.0data alignment switches · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | The Prime Memory System for Array AccessabstractIn this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation. Duncan H. Lawrie, Chandra R. Vora |
IEEE Trans. Computers | 2 |