Demo Data from SIGIR 2026 / reviewers in the wild / expert
Masasada Sato
dblp:51/5436
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorComputer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Interconnection networks and networks-on-chip · 56% Processor architecture and microarchitecture · 19% Parallel and multicore computing · 19% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
load balancing |
0.0 | 1 | 1979 | Dynamic Function Exchanging Mechanism in Poly-Processor System · ISCA 1979 |
Processor architecture and microarchitecture
microprogramming |
0.0 | 1 | 1979 | Dynamic Function Exchanging Mechanism in Poly-Processor System · ISCA 1979 |
Interconnection networks and networks-on-chip › switch architecture
crossbar switch |
0.0 | 1 | 1978 | Interconnection Unit for Poly-Processor System: An Analysis and Design · ISCA 1978 |
Interconnection networks and networks-on-chip
multiprocessor interconnection |
0.0 | 1 | 1978 | Interconnection Unit for Poly-Processor System: An Analysis and Design · ISCA 1978 |
Interconnection networks and networks-on-chip › multiprocessor interconnection
processor-memory interconnection |
0.0 | 1 | 1978 | Interconnection Unit for Poly-Processor System: An Analysis and Design · ISCA 1978 |
Hardware reliability and fault tolerance › processor reliability
processor failure tolerance |
0.0 | 1 | 1979 | Dynamic Function Exchanging Mechanism in Poly-Processor System · ISCA 1979 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | An Integrated Facsimile Mail Service for Office Automation
Naobumi Kanemaki, Masasada Sato, Akira Isoyama |
ICC | 2 |
| 1979 | Dynamic Function Exchanging Mechanism in Poly-Processor SystemabstractMicroprogramming is a basic technique that realizes functionally specialized processors in a functionally distributed multiprocessor system which consists of many small processors. In such a multiprocessor system, it is necessary to change processor functions dynamically in order to back up a heavily loaded processor or a failed processor by a lightly loaded processor. This paper proposes a mechanism for exchanging processor functions in firmware level and shows a hardware organization which realizes the mechanism in an experimental system. In order to clarify the design conditions of an operating system and microprograms, the performance of the mechanism is analyzed from the load balancing point of view. Moreover, the conditions which the mechanism must satisfy are derived. Masasada Sato, Seishi Nishikawa, Ken-ichiro Murakami, S. Takahira |
ISCA | 1 |
| 1978 | Interconnection Unit for Poly-Processor System: An Analysis and DesignabstractThis paper discusses the design of interconnection modules for a multiprocessor system which consists of many small and functionally specialized processors. It is proposed that the information, i.e. programs, data etc., used in the system should be divided into three categories; private information, command data and shared data, according to the analysis of software simulation results. Private information is stored in a memory provided exclusively for each processor. Command data is transferred directly between processors to initiate a function in other processors. Shared data is stored in a memory shared by several processors. For command data and shared data, two different connection modules are provided; the interprocessor connection module using common bus technique, and the processor-memory connection module using crossbar switch technique. The effects of information partitioning on the performance and cost of the system are analyzed. It is verified that the interprocessor connection module technique is preferable than a few possible alternatives through the design analysis and the implementation of a pilot model system. Seishi Nishikawa, Masasada Sato, Ken-ichiro Murakami |
ISCA | 2 |