Student participation in undergraduate research programs has been linked to improved content knowledge, skills, and confidence. However, few research opportunities exist for community college students. This study explores the positive effects of a summer research program on three diverse cohorts of such students. The Transfer-to-Excellence Research Experiences for Undergraduate program is a hands-on summer research internship for California community college students. The program seeks to inspire students to complete a Bachelor’s degree in science or engineering and primarily serves identities underrepresented in those fields. Analysis of mixed methods evaluation data shows that after participating in the program, community college students were better able to find scholarly resources, design ethical scientific experiments, conduct independent research, and analyze data. Additionally, participation in the program enhanced students’ science identity and confidence to pursue further education and careers in science and engineering fields.

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.

This month’s issue offers insight into efficient compression and execution of DNNs, the challenge of connecting rural areas, and the clique problem in wireless communication. which

The International Technology Roadmap for Semiconduc-tors (ITRS) seeks to stimulate invention and research lead-ing to one or more new nanoelectronics technologies that may extend functional scaling of information processing substantially beyond "ultimately scaled" CMOS. Introduction of such new technologies is envisioned in two phases - first by extending the CMOS platform via heterogeneous integration of new technologies and, later, via a replace-ment for CMOS that would provide the equivalent of sev-eral more technology nodes beyond ultimate CMOS. 1D charge state materials (nanotubes and nanowires) appear to be particularly attractive for the first phase. Ferromagnetic or spin-based logic devices are under investigation for the second phase. Some recent work in both of these areas will be presented.

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.