TechViz has been a supporter of Formula Student at KIT for several years reflecting the companys long-term commitment to enhance engineering and education by providing students with powerful VR system software to connect curriculum to real-world applications. Incorporating immersive visualisation and interaction environment into Formula Student vehicle design is proven to deliver race day success, by helping to detect faults and optimise product life cycle. The TechViz LESC system helps to improve the car design despites the short limit of time, thanks to the direct visualisation in the VR system of the CAD mockup and the ease of usage for non-VR experts.

In this paper we evaluate the performance of an SMT processor used as the geometry processor for a 3D polygonal rendering engine. To evaluate this approach, we consider PMesa (a parallel version of Mesa) which parallelizes the geometry stage of the 3D pipeline. We show that SMT is suitable for 3D geometry and we characterize the execution of the geometry stage in term of memory hierarchy, which is the main bottleneck. The results show that latency is not fully recovered by SMT; the use of L2 data prefetching does not succeed in increasing the performance. We show that this problem comes from a pollution of the instruction window by the threads experiencing L2 cache misses, thus reducing the window available for the other threads. We thus propose dcPRED, a hardware mechanism to predict L2 misses and control this pollution. Coupled with L2 data prefetching, dcPRED achieves gains up to 21% over the baseline SMT.

The quality of a real-time high-end virtual reality system depends on its ability to draw millions of textured triangles in 1/60 s. The idea of using commodity PC 3D accelerators to build a parallel machine instead of custom ASICs seems more and more attractive as such chips are getting faster. If image parallelism is used, designers have the choice between two distributions: line interleaving and square block interleaving. Having a fixed block shape and size makes chip design easier. A PC 3D accelerator has a cost-effective external bus and an on-chip texture cache. The performance of such a cache depends on spatial locality. If the image is rendered on multiple engines, this locality is reduced. Locality and load balancing depend on the distribution scheme of the machine. This paper investigates the impact of the distribution scheme on the performance of such a machine. We use detailed cache and memory system simulations with virtual reality benchmarks running on different configurations. We show that: (i) both distributions have the same maximum performance with less than 16 processors, but the square block has a better speedup with 64 processors; (ii) the best SLI (scan-line interleaving) block size depends on the number of processors of the machine and is not suitable for a scalable chip with a fixed block size; and (iii) using a large triangle buffer in the texture mapping engine has a very important impact on the performance.

As technology enables to integrate real-time good quality 30 rendering in a single chip, the classicalproblem of the gap between internal data bandwidth and external memories arisea.The texture mapping function requires a twmendous number of texture accesses and many past implementations have been based on costly high bandwidth external memory.OUT impact study of texture cache used with today's commercial representative 30 software shows that it is possible to render 100 million pixels per second while using an internal cache smaller than 32 KB and a PC memory bus for textures.Texture blocking and number of requests on the cache contribute mainly to those Tesults.Building a high performance parallel subsystem based on such a chip may become an interesting opportunityfor 1eadingpeTformance3D graphic manufacturers though many problems have been observed with caches in parallel machines.As far as texture accesses are concerned, we show that image parallelism generates poor performance with caches.But triangle parallelism scales with multiple rendering processors, each having its own texture cache and the speedup is nearly linear.'A texrl is a pixel in the texture map