This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It combines the strengths of force directed global placement with Mongrel's cell congestion removal to significantly improve the quality of placement during the difficult overlap removal stage of global placement. This is accomplished by using the spreading force in [12] to direct and control Mongrel's ripple move optimization. This new placer is called Force Directed Mongrel (FD-Mongrel). FD-Mongrel also incorporates physical net constraints [26], and improves the congestion model for sparse placements. We propose a new placement flow that uses a limited number of the spreading iterations of [12] to form a preliminary global placement. We then use the new FD-Mongrel described in this paper to remove cell overlaps, while meeting net constraints and optimizing wirelength. We present results on wirelength as well as timing driven placement flows.

We study the problem of performing buffer insertion in the context of a given layout. In a practical situation, there are restrictions on where buffers may be inserted; for instance, it may be possible to route wires over a preplaced macro cell, but may not be possible to insert buffers in that region. As a result, it is desirable to perform route planning and buffer insertion simultaneously. Furthermore it is necessary that such an algorithm be aware of the trade-off between cost (e.g., total capacitance) and delay. In this context we propose the delay reduction to cost ratio (DRCR) problem and present a fast algorithm for the same. Solutions identified by the algorithm are characterized with respect to the overall cost versus performance trade-off curve. Computational experiments demonstrate the viability of the approach.

We study the problem of performing buffer insertion in the context of a given layout in a practical situation, there are restrictions on where buffers may be inserted while routing over such regions may be possible (e.g., due to the presence of macro cells). As a result, it is desirable to perform route planning and biffer insertion simultaneously. Further it is necessary that such an algorithm be aware of the tradeoff between cost (e.g. total capacitance) and delay. In this context we propose the Delay Reduction to Cost Ratio (DRCR) problem and present a fast algorithm for the same. Solutions identified by the algorithm are characterized with respect to the overall cost vs. performance tradeoff curve. Computational experiments demonstrate the viability of the approach.

We give an overview of a standard-cell placer Mongrel. The prototype tool adopts a middle-down methodology in which a grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search "move". Details of this approach including a novel placement legalization procedure are presented. When a global placement has converged, a detailed placement is formed and further optimized by the proposed optimal interleaving technique. Experimental results are presented and are quite promising, demonstrating that there is significant room for improvement in state of the art placement.

This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturally captures blockages, limited routing and wire-sizing resources, layer assignment, etc. Each edge in the multigraph is annotated with resistance and capacitance values associated with the particular wiring segment. The timing-driven maze routing problem is then to find paths which exhibit low resistance-capacitance (RC) delay or achieve a tradeoff between RC delay and total capacitance. An easy-to-implement labeling algorithm is presented to solve the problem along with effective speedup enhancements to the basic algorithm which yield up to 300 times speedup. It is suggested that such an algorithm will become a fundamental tool in an arsenal of interconnect optimization techniques. The tractability of the approach is supported via computational experiments.

This paper presents two primary results relevant to physical design problems in CAD/VLSI through a case study of the linear placement problem.First a local search mechanism which incorporates a neighborhood operator based on constraint relaxation is proposed.The strategy exhibits many of the desirable features of analytical placement while retaining the flexibility and non-determinism of local search.The second and orthogonal contribution is in netlist clustering.We characterize local optima in the linear placement problem through a simple visualization toolthe displacement graph.This characterization reveals the relationship between clusters and local optima and motivates a dynamic clustering scheme designed specifically for escaping such local optima.Promising experimental results are reported.

This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturally captures blockages, limited routing and wire-sizing resources, layer assignment, etc. Each edge in the multigraph is annotated with resistance and capacitance values associated with the particular wiring segment. The timing-driven maze routing problem is then to find paths which exhibit low resistance-capacitance (RC) delay or achieve a tradeoff between RC delay and total capacitance. An easy-to-implement labeling algorithm is presented to solve the problem along with effective speedup enhancements to the basic algorithm which yield up to 300 times speedup. It is suggested that such an algorithm will become a fundamental tool in an arsenal of interconnect optimization techniques. The tractability of the approach is supported via computational experiments.