Toshiaki Kitamura

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4ranked-venue papers

0as first author

0since 2021 · last 2004

0000-0002-0819-2970ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Processor architecture and microarchitecture · 99% High-performance computing · 1%

Topics — the 6 heaviest of 6, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Processor architecture and microarchitecture › instruction scheduling dynamic instruction scheduling	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture instruction scheduling	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture superscalar processor	1	2001	A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture instruction-level parallelism	1	1983	A User-Microprogrammable, Local Host Computer With Low-Level Parallelism · ISCA 1983
Processor architecture and microarchitecture › microprogramming microprogrammable processor	1	1983	A User-Microprogrammable, Local Host Computer With Low-Level Parallelism · ISCA 1983
High-performance computing scientific computing systems	1	1983	A User-Microprogrammable, Local Host Computer With Low-Level Parallelism · ISCA 1983

Methods — techniques the papers use, named apart from their topics

dynamic scheduling scheme · 0.0microprogramming · 0.0

Year	Publication	Venue	Position
2004	A MATLAB-Based Code Generator for Sparse Matrix Computations Hideyuki Kawabata, Mutsumi Suzuki, Toshiaki Kitamura	APLAS	3
2001	A high-speed dynamic instruction scheduling scheme for superscalar processors Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori	MICRO	3
1995	Scalar Processor of the VPP500 Parallel Supercomputer abstract Article Free Access Share on Scalar processor of the VPP500 parallel supercomputer Authors: Yasuhiko Nakashima Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, Japan Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, JapanView Profile , Toshiaki Kitamura Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, Japan Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, JapanView Profile , Hideo Tamura Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, Japan Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, JapanView Profile , Masaaki Takiuchi Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, Japan Fujitsu Limited, 1015 Kamikodanaka, Nakahara-ku Kawasaki 211, JapanView Profile , Kenichi Miura Fujitsu America Inc, 3055 Orchard Dr, M/S 1-5, San Jose, CA Fujitsu America Inc, 3055 Orchard Dr, M/S 1-5, San Jose, CAView Profile Authors Info & Claims ICS '95: Proceedings of the 9th international conference on SupercomputingJuly 1995 Pages 348–356https://doi.org/10.1145/224538.224624Published:03 July 1995Publication History 2citation235DownloadsMetricsTotal Citations2Total Downloads235Last 12 Months23Last 6 weeks7 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF Yasuhiko Nakashima, Toshiaki Kitamura, Hideo Tamura, Masaaki Takiuchi, Ken'ichi Miura	International Conference on Supercomputing	2
1983	A User-Microprogrammable, Local Host Computer With Low-Level Parallelism abstract This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the marriage of high-speed, parallel processing capability offered by four powerful Arithmetic and Logic Units (ALUs) with architectural flexibility provided by large scale, dynamic user-microprogramming. By changing its writable control storage dynamically, the QA-2 can be tailored to a wide spectrum of research-oriented applications covering high-level language processing and real-time processing. Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata 0001, Hiroshi Hagiwara	ISCA	3