Guided image filtering has been applied widely in recent years as a solution to the ever-increasing demand of high-performance filtering, especially for real-time image/video processing. The lately proposed gradient domain guided image filter (GDGIF) is one of the typical works focusing on improving the quality of the filtering result of the original guided image filter (GIF), dealing with the halo-artifacts problem for edge-preserving smoothing. However, due to the involvement of global pixel values in the computation, high computation complexity, and additional complex operation, there is no existing VLSI design for the gradient guided filter. This paper presents a high-throughput VLSI architecture for real-time full-HD (1920×1080) GDGIF. Four techniques are used in the newly proposed design to reduce the computation complexity and increase the processing throughput. First, a pre-processing stage is introduced to address the problem of global parameters required in the GDGIF. Second, multi-scale down-samplings are adopted for reducing circuit size and processing time. Then, a parallel structure operated at a higher frequency is used at the output stage to restore the full image size and to achieve high throughput at the same time. At last, approximated computation is introduced to eliminate speed bottleneck by simplifying the complex exponentiation operation. Based on the STM 65-nm CMOS technology, the implementation results show that the proposed architecture is able to support full-HD image filtering at a throughput above 75 frame/s, with a design area of 586314 μm2and a power consumption of 18.5 mW.

In modern symmetrical chip multiprocessor (CMP) architecture, problems in cache coherence, context switch overheads and serialized code bottleneck are major causes of excessive computing power dissipation in the application of simultaneous multithreading (SMT) technique. This research models and manages above-mentioned problems based on user application usage patterns identified in a mobile computing platform. A novel scheduler has been developed to realize power management schemes based on the Linux kernel (version. 3.0.1) and deployed in Android 4.0 ICS. The scheduler monitors multiple system performance metrics and predicts power dissipation based on the historical user application usage values as well as the content of the scheduler run queue. The length of the time slices and the variables of process control blocks are adjusted to optimize power dissipation according to the prediction. The proposed scheduler module has achieved a power dissipation reduction of 13 to 24% in a GEM5 simulated environment.

High performance filtering has been in ever increasing demand for a range of applications, especially for real-time image/video processing. Guided image filter is one of the widely used image filters. Among them, the gradient domain guided image filter for edge-preserving smoothing and for mitigating the halo-artifacts problem existed in the current guided image filters is reported recently. Due to its computation complexity and the requirement of global pixel values in the computation, there is no existing VLSI implementation of gradient domain guided image filter. This paper presents such a VLSI architecture incorporated with techniques to reduce computation complexity and increase processing throughput. Subsampling technique is adopted in the design to save computation cost in terms of size and power consumption, without visually hampering the filtering result. Parallel structure is used at the output stage to restore the full image size and to achieve high throughput. Based on the STM 90-nm CMOS technology, the synthesis result shows that the proposed architecture is able to support Full-HD (1920 × 1080) image filtering at a throughput above 60 frame/s, with a design area of 726671.6μm2and power consumption of 9.85mW. Compared to the existing design, it can achieve two times higher throughput, and has 11.25% smaller size and 56.3% lower power consumption.

Unlike the existing designs that improve the memory efficiency by reducing the on-chip memory words, we propose a memory-efficient 2-D DWT architecture which improves the memory efficiency by reducing the wordlength of the on-chip memory. Based on our recently proposed memory-efficient 2-D DWT architecture, which achieves the highest memory efficiency among the existing designs, we analyze the dynamic range and optimize the required integer bit (IB) width of every internal signal for memory reduction. We construct an architecture-specific accuracy model for both 9/7 and 5/3 2-D DWT and optimize the factional bit (FB) width of every internal signal without sacrificing the precision of the output. Theoretical estimation shows a 17.5% reduction of the temporal memory regardless of input image size and throughput. In addition, the arithmetic resource is reduced. The synthesis results in 90-nm CMOS show a better area-delay product (ADP) of 25.1% over the best existing design.

This paper presents a novel method named the Unified Mitchell-based Approximation (UMA) to obtain an optimized Mitchell-based logarithmic conversion circuit for any desired conversion accuracy up to 14 bits. UMA is the first method that is able to obtain a conversion circuit when a specific accuracy is required. In this work, we studied and analyzed five design parameters and their impact on accuracy and hardware merits. We formulate the hardware model of the error correction circuit in the conversion circuit for performance evaluation. Given an accuracy requirement, the proposed method explores the design space of the five design parameters. As the design space is theoretically huge, we propose constraints for the range of the parameter values and develop a systematical search algorithm for exploring the design space. UMA is able to obtain an area-delay product optimized circuit for each of the conversion accuracies achieved by the existing Mitchell-based designs. Synthesis results in 90 nm CMOS technology show that the circuits obtained are comparable or better than the existing Mitchell-based designs with the same accuracy objective. Nine of the fifteen circuits obtained achieve better area-delay product by more than 50 percent. In addition, UMA is able to obtain circuits for any accuracy from 4 to 14 bits, while the best accuracy achieved by the existing Mitchell-based methods is less than 12 bits.

A novel non-iterative circuit for computing division based on logarithm is proposed in the paper. Mitchell-based methods are used for the logarithmic and antilogarithmic conversions. Merging the conversion stages in the implementation is not possible if the existing antilogarithmic conversion algorithms are used. Thus, the critical path has at least two carry propagate adders (CPAs). This work introduces a new antilogarithmic algorithm to merge the two conversion stages into a single one to remove one of the two CPAs. Compared to the best existing Mitchell-based logarithmic division computation method used in a 3-D graphic system, the proposed design achieves improvements by 45.4% and 34.8%, respectively, in computation speed and area-delay product with an area overhead of 19.5%.

The tables-and-additions methods for accurate computation of elementary functions are fast in computation speed but require large memory. A memory-efficient method named as the integrated Add-Table Lookup-Add (iATA) is proposed in this paper. In iATA, the mathematical formulation for computing the elementary functions is derived without using the central difference formulation to save memory. Three additional techniques, specifically the carry select technique, symmetry property exploitation and unequal partitioning of input with the aid of error analysis, are integrated in iATA to further reduce the memory size. The experimental results show that the proposed method is able to achieve higher memory efficiency than the best existing tables-and-additions methods. For the reciprocal and the natural logarithm function, iATA saves 23.63 and 61.39 percent of memory when compared to the best existing results obtained, respectively, by the unified Multipartite Table Method [39] and the Symmetric Table Addition Method [37].

A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16-bit integer input.

A novel approach of designing serial-serial hybrid multiplier is proposed for applications with high data sampling rate ( ≥4 GHz). The conventional way of partial product formation is revamped. Our proposed technique effectively forms the entire partial product matrix in justnsampling cycles for ann×nmultiplication instead of at least 2ncycles in the conventional serial-serial multipliers. It achieves a high bit sampling rate by replacing conventional full adders and 5:3 counters with asynchronous 1's counters so that the critical path is limited to only an and gate and a D flip-flop (DFF). The use of 1's counter to column compress the partial products preliminarily reduces the height of the partial product matrix fromnto [log2n] +1, resulting in a significant complexity reduction of the resultant adder tree. The proposed hybrid column compressed multiplier consists of a serial-serial data accumulation unit and a parallel carry save adder (CSA) array that occupies approximately 35% and 58% less silicon area than the full CSA array multiplier with operands of wordlength 32 × 32 and 64 × 64, respectively. The post-layout simulation results based on 90-nm seven metal single poly CMOS process technology shows that our 64 × 64 multiplier dissipates 39% less average power at a sampling rate of 4 GHz, and has only 11% additional delay penalty to complete a multiplication compared to the conventional fully parallel CSA array multiplier.

This paper presents a new methodology of multiplierless implementation of inner-product computation. The inner-product computation is decomposed to form an architecture that facilitates an efficient serial accumulation of the 1's in the partial product matrix of each multiplication of a pair of elements from the input vectors. The 1's that appear at each partial product position are accumulated by a serial D flip flop (DFF) based 1's counter. This accumulation stage reduces the column height of the partial product matrix by transforming L vertical bits to ⌊log2L⌋ + 1 horizontal bits at each coordinate of the partial product matrix. The counter outputs are further summed using carry save addition based on Dadda's reduction algorithm followed by final carry propagating addition to obtain the final inner-product result. As the counter can operate at a frequency of 2 GHz when implemented on TSMC 0.18 μm CMOS process, the accumulation time is reduced significantly. With simpler partial product reduction tree, the hardware complexity is substantially reduced while the throughput is maintained to be comparable or better than many existing parallel inner-product computation architectures. The synthesis results of the proposed inner-product architecture for various inner-product lengths show that it has lower area-delay-product than many existing architectures.

This paper proposes a new design methodology to reduce the logic complexity of reconfigurable multiplier block (ReMB). The minimization problem is modeled as a scheduled time-multiplexed data flow graph (TDFG). To reduce the number of operators to be scheduled in the DFG, the most dominant common subexpressions are greedily identified and eliminated based on the subexpressions' frequencies which are updated dynamically in the optimization process. High level synthesis algorithm is then employed to perform the scheduling of operators to control steps. By binding the compatible operators in the same control steps, more operators can be saved. Two design examples are used to demonstrate the effectiveness of the proposed algorithm. On average, the logic complexity of the proposed ReMB design is about 19% lower than that of the classical ReMB methods, and 7% lower than that of the latest and most competitive ReMB design methodology.

In this paper, an algorithm named MuVoF is proposed to perform multivoltage multifrequency low-energy high-level synthesis for functionally pipelined datapath under resource and throughput constraints. A datapath is partitioned into a number of pipelined stages such that the clock period can be extended maximally. A multivoltage assignment algorithm then utilizes the extended clock period to reduce energy by lowering the supply voltages of the resources. The results are further refined by four local transformations performed in an iterative process. The experiment results show that MuVoF is capable of exploring the design space effectively and achieves efficient energy reduction.

In this paper, a new efficient algorithm is proposed for the synthesis of low-complexity finite-impulse response (FIR) filters with resource sharing. The original problem statement based on the minimization of signed-power-of-two (SPT) terms has been reformulated to account for the sharable adders. The minimization of common SPT (CSPT) terms that were considered in our proposed algorithm addresses the optimization of the reusability of adders for two major types of common subexpressions, together with the minimization of adders that are needed for the spare SPT terms. The coefficient set is synthesized in two stages. In the first stage, CSPT terms in the vicinity of the scaled and rounded canonical signed digit (CSD) coefficients are allocated to obtain a CSD coefficient set, with the total number of CSPT terms not exceeding the initial coefficient set. The balanced normalized peak ripple magnitude due to the quantization error is fulfilled in the second stage by a local search method. The algorithm uses a common-subexpression-based hamming weight pyramid to seek for low-cost candidate coefficients with preferential consideration of shared common subexpressions. Experimental results demonstrate that our algorithm is capable of synthesizing FIR filters with the least CSPT terms compared with existing filter synthesis algorithms.

Optimizing adder cost for the implementation of finite-impulse response (FIR) filter has been an area of active research. The prevailing algorithms for the design of fixed point FIR filters have decoupled the filter coefficient synthesis from common subexpression elimination. This paper presents a new algorithm for the design of low-complexity FIR filters with resource sharing to reduce the adder cost directly during the coefficient synthesis process. The original problem statement based on the minimization of signed-power-of-two (SPT) terms is recast to account for the physical adder cost oriented common signed-power-of-two (CSPT) terms. Experimental results demonstrate that our algorithm is capable of synthesizing FIR filters with the least CSPT terms compared with existing filter synthesis algorithms

This paper presents an architecture for matrix multiplication implemented on reconfigurable hardware with partially reconfigurable feature. The proposed design significantly reduces the size and achieves the minimum computation cycles for the n /spl times/ n matrix multiplication. Compared with the linear array design (Jang et al., 2002) the area of our design is reduced by 72%-81% while the AT metrics (product of area and latency) is reduced by 40%-58% for matrix size between 3 /spl times/ 3 and 48 /spl times/ 48. The versatility of our design is demonstrated in different parameterisable instantiation to cater for different implementations with various time and area requirements. Partially reconfiguration allows us to reload the design contents with the minimum configuration overhead. The performance of our design is even better for larger matrices.

A contention resolution algorithm (CRA) is proposed for the common subexpression elimination of the multiplier block of the digital filter structure. CRA synthesizes common subexpressions of any Hamming weight to achieve an overall minimization with the emphasis that every logic depth increment must be accompanied by a reduction in logic complexity. A new data structure, called the admissibility graph is introduced to represent succinctly a set of coefficients; the admissible subexpressions are progressively labeled on the graph as either precedence or contention edges (or paths). The performance of CRA is evaluated based on benchmarked circuits and randomly generated coefficients. It is demonstrated that our algorithm outperforms several distinguished algorithms in both the logic depth and logic complexity.

In a realistic register-transfer-level component library, there usually exist several different hardware implementations for one generic function. This gives rise to a large design space of component selection which is interleaved with the scheduling of operations. Previous methods ignored the presence of multicomponent selection in the process of lower/upper hound estimation of scheduling, and produced the local lower/upper bounds which would cause the suboptimum designs. Opposite to the previous methods, we compute, in this paper, the lower/upper bounds which consider scheduling and component selection simultaneously. A new problem of multicomponent selection integrated with interval scheduling is studied. We present a very interesting and important result that both the lower bound and upper bound of multicomponent selection are obtained on the most cost-effective components which have the minimum area-delay products. This property leads to the fact that the lower bound and upper bound of multicomponent selection can be calculated efficiently. An integer linear programming model and a surrogate relaxation technique are proposed to derive an optimum surrogate lower bound which has an asymptotic performance ratio less than two for a single type of function. An upper bound with the same asymptotic performance ratio is also obtained which turns out to be the optimum solution value of the traditional unicomponent selection with the most cost-effective components. Both the theoretical analysis and the experimental results show that the performance of the bounds are very promising.

A new algorithm named the time-zone algorithm for solving register allocation problem in the automatic data path synthesis is presented in this paper. The time-zone algorithm was developed from the left-edge algorithm with which the number of registers can be minimized. The time-zone algorithm was developed to minimize the number of registers as well as the interconnections and the number of multiplexers required for the registers. The experimental results obtained from testing several published examples show that the interconnections are improved and the number of multiplexers is reduced while at the same time the number of registers is still minimized.>