Power scaling in FPGA can be enabled with support for distributed configurable voltage domains and block-level control. Each configurable logic block (CLB) represents a unique power domain tile on the chip. Each tile can be configured independently to operate at high VDD, low VDD, or disabled. In this work, a customized design flow to support multiple on-chip voltage domains leverages existing commercial tools Astro and standard cell library enhanced with a few additional cells for power management. In this paper, the authors developed a power-aware place and route-tool to determine which non-critical paths can run at reduced voltage and to configure the various domains of the array accordingly. By introducing fine-grain hardware controls, power-aware FPGA forms the basis for a platform that allows for effective in-system energy delay tradeoffs for energy-constrained applications such as handheld wireless systems.

This work showcases a power-aware system design methodology for DSP applications on reconfigurable hardware platforms. In particular, an enhanced FPGA architecture is proposed and analyzed for a deep submicron process technology. These enhancements reduce Configurable Logic Block (CLB) usage for distributed arithmetic implementations of signal processing applications by 50% or more thereby reducing the load on interconnect resources. Multi-Threshold CMOS (MTCMOS) circuit design techniques are aggressively applied to reduce subthreshold leakage using an auto power-down feature for unused logic. Results show a 14x reduction in leakage current for unused CLBs or CLBs in deep sleep mode. CLBs in active mode see up to 2.8x steady-state power reduction. A testchip demonstrating these techniques in 0.13 micron technology has been sent out for fabrication.

Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 /spl mu/m, dual V/sub T/ test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2/spl times/ (measured) for some CLB configurations.

This paper discusses the design tradeoffs and implementation options for building wideband CDMA systems. System on a chip (SOC) solutions have a range of implementation options, from processor cores to custom ASIC (or a mix of both), to satisfy the extremely challenging requirements of the digital baseband of a next generation wireless system. Additionally, good designs should have a roadmap that will take advantage of rapid improvements in process technology. This paper describes the use of coprocessors alongside DSPs to meet the demanding computational requirements of WCDMA. We show that a coprocessor based design still achieves reasonably efficient area and power use, maintains a high degree of programmability and has a good technology migration path.

Many standardized hardware communication interfaces offer runtime flexibility and configurability at the cost of efficiency.An alternate approach is the use of a highly-efficien~minimal communication element with as much communication decision-making as possible done at compile time.NuMesh is a packaging and interconnect technology supporting high-bandwidth systolic communications on a 3D nearest-neighbor lattice; our goal is to combine Lego-like modularity with supercomputer performance.To date, the primary focus of the project has been the class of applications whose static communication patterns can be precompiled into independent and carefully choreographed finite state machines running on each node.Several extensions of the NuMesh to more general communication paradigms have been implemented, and the issues involved are under active exploration.This paper presents an overview of our approach, as well as an introduction to our current-generation prototype.We also discuss our software environment and simulation technology, and enumerate some of the applications and programming models we have developed to make full use of the capabdities of the NuMesh.