This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).

Design of reliable chips with high yield is an extremely challenging task in UDSM technologies. Time to market pressures, which often limit the necessary verification before tape-out, typically are manifested as ramp-to-production problems on “good” designs either in the manufacturing process or in the field. Burn-in process, a reactive measure to ship reliable chips, is not effective for high volume designs. Another cause for concern is hidden failures that go undetected due to incompleteness of test vectors.

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an efficient approach for the verification of power distribution at the full-chip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples will be provided. We will also demonstrate the necessity of an analysis at the full-chip transistor level to verify the complex interactions between different design blocks based on static and dynamic effects.

This tutorial describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems before tape-out. We first illustrate that UDSM verification must go well beyond simple geometric and circuit comparison checks to address increasingly important issues such as timing, power integrity, signal integrity, and reliability. The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described. We present real-world examples of such problems and how to find these problems using full-chip verification.

Power distribution design in high-performance chips is a task that is not eased through the application of power reduction techniques. Although the average power of a high-performance design can be reduced, the peak to average power current ratio of blocks increases as a result, aggravating the challenges faced prior to average power reduction. This paper discusses the power distribution design challenge: to reliably deliver a predictable voltage to all transistors under all operating conditions. Steps in power estimation, approaches to power distribution implementation, and verification of power distribution are reviewed. The myths versus reality of power distribution design in high-performance chips are provided.

The performance of dynamic mixed-mode simulation depends upon the modes of simulation used and the duration of simulation at each mode. The requirements for automatic dynamic mixed-mode simulation are stipulated. A new approach is presented to perform dynamic mixed-mode simulation in a static mixed-mode simulation environment using network reconfiguration. The approach is implemented in Lsim, a commercially available mixed-mode simulation environment. A performance increase of an order of magnitude in speed is observed even for small circuits.

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors have not been previously provided. Errors, if secondary effects are not addressed, may total 100% or more. The significant improvement in simulation accuracy using these proposed techniques is shown.

This paper presents new techniques for accurately accounting for RC-interconnect effects in conjunction with nonlinear MOS macromodeling. RC-interconnects contribute to the delay of signals, but more importantly, they alter the shape of signals. Thus, circuit performance is affected by nonlinear transistors, secondary MOS effects, input waveform shape, and RC-interconnect loading. All these issues are addressed by the techniques presented here. An equivalent /spl pi/-model for RC-interconnects is used in combination with advanced nonlinear MOS macromodeling to provide simulation results with accurate timing and, more critically, waveform shape of the gate output. Thus, the macromodel provides accurate simulation results whether the behavior is dominated by the nonlinear transistors or RC-interconnects. These techniques yield accurate circuit behavior at speeds two orders of magnitude faster than SPICE for even small circuits.

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. The significant improvement in simulation accuracy using these proposed techniques is shown. The timing macromodel used to implement these techniques is up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels. The accuracy of this macromodel over a wide range of operating conditions is demonstrated. The macromodel and reduction techniques can be used to minimize VLSI simulation time, provide fast feedback in circuit optimization, and generate accurate data for higher-level macromodels. The proposed reduction techniques apply to linear and nonlinear macromodels.>

A novel technique is introduced for automatically performing mixed-mode timing simulation of MOS circuits. A SPICE2 circuit description is assumed to be given, the circuit is first partitioned into channel-connected subcircuits. Each subcircuit is then examined and is statically classified as digital or analog if one of many configurations is detected. Subcircuits which contain memory cells, sense amplifiers, or internal feedback are automatically classified as analog. Any user-specified analog subcircuits are classified as analog. Analog subcircuits are simulated using detailed electrical simulation while digital subcircuits are simulated using fast timing simulation with a ramp waveform representation. Fast timing simulation uses a nonlinear macromodel to model the charging and discharging of subcircuit output nodes. State transitions are initially modeled using a single ramp. Static and dynamic mode selection are used to ensure that accuracy is retained during simulation while minimizing simulation time. The implementation of these techniques in IDSIM2 is discussed. Examples of automatic mixed-mode timing simulation are presented.>

The approach accounts for RC parasitic loading, overlapping inputs, and incomplete charging or discharging of output nodes. The macromodeling splits the subcircuits data into transistor-gate information and loading information. In a given design many subcircuits have identical gate configurations, but each instance of a gate has a unique RC loading condition. During simulation the gate and loading information is combined and used to calculate output-node voltage changes. All necessary information needed for voltage calculations are precomputed and stored in tables. The proposed macromodeling and the delay method greatly reduce simulation time. The approach has been implemented in a simulator called IDSIM2, and a number of large examples have been simulated. Speedups of up to three orders of magnitude have been obtained compared to standard circuit simulation, with loss of accuracy of less than 10%.>