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Gerhard E. Hoernes

dblp:56/4275 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1968
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 62% Processor architecture and microarchitecture · 38%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › resource management
memory management
0.011968
Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968
Emerging computing paradigms › neuromorphic computing
associative memory
0.011968
Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968
Processor architecture and microarchitecture › microprogramming
control store
0.011968
Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968
Processor architecture and microarchitecture
microprogramming
0.011968
Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor · IEEE Trans. Computers 1968

Methods — techniques the papers use, named apart from their topics

read-only control storage · 0.0
YearPublicationVenuePosition
1968 Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor
abstract
Abstract—The Cambridge System, comprising a standard IBM System/360 Model 40 and an associative memory, is described from the viewpoint of its implementation using the READ-only control storage of the Model 40. In particular, we discuss the use of the ROS in 1) controlling the flow of data between the CPU and the associative memory registers, and 2) handling translation control, absent page indications, and variable field operand pretesting, when the associative memory is used for page translation in a time-sharing mode of operation. Although the main use of the system is as a computer facility that may be shared simultaneously by up to fifteen users, it may also be used as an ordinary batch processor having a small experimental associative memory among its facilities. The magnitude of the ROS additions and modifications, in terms of numbers of microinstructions, is given.
Leo Hellerman, Gerhard E. Hoernes
IEEE Trans. Computers2