In this paper, we explore a low area-time elliptic curve point multiplication (ECPM) hardware accelerator over Curve25519. Firstly, we analyze the correlation of the data hazards of LADDER (main operation), the number of pipeline stages in modular multiplication (MM), and the number of iterations of multiplier in MM, and then establish an equation among them. Based on this equation, a new iterative hardware model of modular multiply-accumulator (MMAC) with stage=10 using a 128-bit multiplier, and a new LADDER scheduling are proposed to support high-performance scenarios for Curve25519 ECPM. Secondly, based on the proposed method, we propose a new 255-bit iterative MMAC. Finally, we explore the trade-off between area and time, present an efficient hardware design to accelerate the Curve25519 ECPM. The proposed accelerator is implemented on the Xilinx XC7Z020 platform. The results show that the proposed accelerator costs 2,367 Slices and 36 DSP blocks, with a clock frequency of 298 MHz. When calculating one Curve25519 ECPM, compared to previous designs with the best area*time (AT) value, the AT value of this design is 220% superior to their design, while the area and time have improved by 52% and 108% compared to theirs, respectively.

This paper explores more efficient LUT6-Based multiplier for Montgomery Modular Multiplication (MMM) on FPGA. Firstly, we analyze and compare the LUT6-Cost of multipliers using previous Radix-4/8/16 Booth methods. Based on the LUT6, we propose an improved LUT6-Based Radix-16 Booth method for Coarsely Integrated Operand Scanning (CIOS) MMM. When the value of multiples remains unchanged for a period of time, this method uses LUT6-Based SDP-RAM to store multiples instead of MUX to select, which effectively reduces the LUT6-Cost of Decode. Secondly, we propose a new LUT6-Based CIOS MMM using the proposed method. Finally, we explore the trade-off between area and latency, present an efficient LUT6-Based MMM hardware design (LUT6-MM) to accelerate CIOS MMM. The LUT6-MM is a scalable, parametric, and reconfigurable design, it is implemented on Xilinx Virtex-7 FPGA. When performing 1024/2048-bit MMM, the results show that the area*latency products (ALPs) of LUT6-MM (w1=32,w2=128) are 51.1%/48.8% of the previous state-of-art scalable and parametric LUT6-Based reference (Non-Reconfigurable, Not using DSP).

Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize$w$=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively.