The value of semiconductor-based systems continues to increase rapidly especially when considering the cost associated with building it. As such, Moore's Law has become a law associated broadly with value growth instead of pure performance growth. While semiconductor nodes continue to provide value albeit at a slower rate, it is design factors that ensure value is indeed filtered down to the final product. In this paper we assess the impact of architecture improvements in the value trends associated with key industry drivers such as mobile (smartphone) systems. We attempt to measure the delivered value and to understand the contribution of Architecture as a fundamental engine for improvement in coming decades.

The International Technology Roadmap for Semiconductors (ITRS) has roadmapped technology requirements of the semiconductor industry over the past two decades. The roadmap identifies major challenges in advanced technology and leads the investment of research in a cost-effective way. Traditionally, the ITRS identifies major semiconductor IC products as drivers; these set requirements for the state-of-the-art semiconductor technologies. High-performance microprocessor unit (MPU-HP) for servers and consumer portable system-on-chip (SOC-CP) for smartphones are two examples. Throughout the history of the ITRS, Moore's Law has been the main impetus for these drivers, continuously pushing the transistor density to scale at a rate of 2× per technology generation (aka “node”). However, as new requirements from applications such as data center, mobility, and context-aware computing emerge, the existing roadmapping methodology is unable to capture the entire evolution of the current semiconductor industry. Today, comprehending how key markets and applications drive the process, design and integration technology roadmap requires new system-level studies along with chip-level studies. In this paper, we extend the current ITRS roadmapping process with studies of key requirements from a system-level perspective, based on multiple generations of smartphones and microservers. We describe potential new system drivers and new metrics, and we refer to the new system-level framing of the roadmap as ITRS 2.0.

In addition to designing the functionality, today’s SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology techniques for enhancing manufacturability, yield and reliability or "DFX" to include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques. Then, it concentrates on several examples of each of these techniques.

High-speed communications link cores must consume low-power, feature low bit-error-rates (BER), and address many applications. We present a methodology to design adaptive link architectures, whereby the link's internal logic complexity, frequency, and supply are simultaneously adapted to application requirements. The requirement space is mapped to the design space using requirements measurement circuits and configurable logic blocks. CMOS results indicate that power savings of 60 versus the worst case are possible, while the area overhead is kept under 5.

Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000-gate 3.2-Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2V to 0.95V, the chip demonstrates power savings of over 25%.

Significant acceleration of todays complex collaborative design processes can be achieved if team members are able to apply search heuristics that consider the simultaneous effect of all design constraints. We present the Active approach to Design Process Management (ADPM), whereby designers receive constraint-based feedback that enables them to apply these search heuristics effectively. To evaluate ADPM, we developed a design process evaluation environment called TeamSim. Evaluation results suggest that ADPM can reduce costly design iterations at the expense of extra, less costly, verification tool executions.

Today's complex design processes feature large numbers of varied, interdependent constraints, which often cross interdisciplinary boundaries.Therefore, a computersupported constraint management methodology that automatically detects violations early in the design process, provides useful violation notification to guide redesign efforts, and can be integrated with conventional CAD software can be a great aid to the designer.We present such a methodology and describe its implementation in the Minerva II design process manager, along with an example design session.