Demo Data from SIGIR 2026 / reviewers in the wild / expert
Soumyendu Raha
dblp:57/4634
· DBLP profile ↗
5ranked-venue papers
0as first author
2since 2021 · last 2022
0000-0003-3530-7507ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 3 · 2 since 2021Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 36% High-performance computing · 36% Reconfigurable computing and FPGAs · 28% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › scientific computing accelerator
linear algebra accelerator |
0.3 | 1 | 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization · IEEE Trans. Parallel Distributed Syst. 2018 |
High-performance computing › numerical linear algebra › matrix factorization
QR factorization |
0.3 | 1 | 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization · IEEE Trans. Parallel Distributed Syst. 2018 |
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable data-path |
0.3 | 1 | 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization · IEEE Trans. Parallel Distributed Syst. 2018 |
Hardware accelerators and domain-specific architectures
algorithm-hardware co-design |
0.1 | 1 | 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization · IEEE Trans. Parallel Distributed Syst. 2018 |
High-performance computing › numerical linear algebra
dense linear algebra |
0.1 | 1 | 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization · IEEE Trans. Parallel Distributed Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
algorithm-architecture co-design · 0.3DAG analysis · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Computationally-Efficient Bandwise GBM Model for Hyperspectral Nonlinear UnmixingabstractNonlinear Unmixing using the Band-wise Generalized Bilinear Mixing (NU-BGBM) model specifies an acceptable mixing scenario up to the second-order interaction of light rays and also suppresses various types of mixed noise while performing un-mixing. However, NU-BGBM requires high computational time and multiple parameter tuning, which could practically limit its application to large HyperSpectral Images (HSIs). In this context, we propose a computationally efficient BGBM as a fast and robust variant of the NU-BGBM method, In this model, the objective function for the non-linear optimization scheme is designed without the sparsity constraint, and an iterative scheme based on the Alternating Direction Method of Multipliers (ADMM) is formulated for solving the proposed model. Extensive analyses have been carried out on synthetic (with simulated mixed noise) and real HSIs. The performance of the proposed method was compared with the NU-BGBM model using signal-to-reconstruction error (SRE), abundance Root-Mean-Square Error (aRMSE), source Root-Mean-Square Error (sRMSE), and Root-Sum-Squared (RSS) error. Results from extensive numerical analysis reveal that the proposed method reduces computation time (on an average six times faster) while being comparable (and often better) than NU-BGBM in terms of accuracy on large data sets. Touseef Ahmad, Soumyendu Raha, Rosly Boy Lyngdoh, Anand S. Sahadevan, Arundhati Misra 0001 |
IGARSS | 2 |
| 2021 | Robust Coupled Non-Negative Matrix Factorization for Hyperspectral and Multispectral Data FusionabstractIn recent time, Hyperspectral(HS) and multispectral(MS) data fusion based on spectral unmixing methods has become an active area of research. Coupled non-negative matrix factorization (CNMF), one among many unmixing-based data fusion approaches, performs alternating unmixing of the HS and MS data while connecting the results by point spread function and spectral response function of the sensors. However, CNMF operates exclusively on the spectral information of the HS and MS data and also disregards the spatial distribution of the data. In this paper, we propose an extended linear mixing model approach to enhance the spatial resolution of HS data. The proposed method extends the commonly used linear mixing model for data fusion by introducing an additional term that accounts for the non-linearity effects as well. The results of the simulation obtained from the analysis on various synthesized datasets suggest that the proposed method can significantly improve the Peak signal-to-noise ratio (PSNR), minimize the relative dimensionless global error (ERGAS) of fusion, and also competes with state-of-the-art approaches. Touseef Ahmad, Rosly Boy Lyngdoh, Anand S. Sahadevan, Arundhati Misra 0001, Soumyendu Raha |
IGARSS | 6 |
| 2018 | Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR FactorizationabstractQR factorization is a ubiquitous operation in many engineering and scientific applications. In this paper, we present efficient realization of Householder Transform (HT) based QR factorization through algorithm-architecture co-design where we achieve performance improvement of 3-90x in-terms of Gflops/watt over state-of-the-art multicore, General Purpose Graphics Processing Units (GPGPUs), Field Programmable Gate Arrays (FPGAs), and ClearSpeed CSX700. Theoretical and experimental analysis of classical HT is performed for opportunities to exhibit higher degree of parallelism where parallelism is quantified as a number of parallel operations per level in the Directed Acyclic Graph (DAG) of the transform. Based on theoretical analysis of classical HT, an opportunity to re-arrange computations in the classical HT is identified that results in Modified HT (MHT) where it is shown that MHT exhibits 1.33x times higher parallelism than classical HT. Experiments in off-the-shelf multicore and General Purpose Graphics Processing Units (GPGPUs) for HT and MHT suggest that MHT is capable of achieving slightly better or equal performance compared to classical HT based QR factorization realizations in the optimized software packages for Dense Linear Algebra (DLA). We implement MHT on a customized platform for Dense Linear Algebra (DLA) and show that MHT achieves 1.3x better performance than native implementation of classical HT on the same accelerator. For custom realization of HT and MHT based QR factorization, we also identify macro operations in the DAGs of HT and MHT that are realized on a Reconfigurable Data-path (RDP). We also observe that due to re-arrangement in the computations in MHT, custom realization of MHT is capable of achieving 12 percent better performance improvement over multicore and GPGPUs than the performance improvement reported by General Matrix Multiplication (GEMM) over highly tuned DLA software packages for multicore and GPGPUs which is counter-intuitive. Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy 0001, Ranjani Narayan |
IEEE Trans. Parallel Distributed Syst. | 4 |
| 2014 | Performance metrics in a hybrid MPI-OpenMP based molecular dynamics simulation with short-range interactions
Anirban Pal, Abhishek Agarwala, Soumyendu Raha, Baidurya Bhattacharya |
J. Parallel Distributed Comput. | 3 |
| 2014 | Rollover-Preventive Force Synthesis at Active Suspensions in a Vehicle Performing a Severe Maneuver With Wheels Lifted OffabstractAmong the intelligent safety technologies for road vehicles, active suspensions controlled by embedded computing elements for preventing rollover have received a lot of attention. The existing models for synthesizing and allocating forces in such suspensions are conservatively based on the constraints that are valid until no wheels lift off the ground. However, the fault tolerance of the rollover-preventive systems can be enhanced if the smart/active suspensions can intervene in the more severe situation in which the wheels have just lifted off the ground. The difficulty in computing control in the last situation is that the vehicle dynamics then passes into the regime that yields a model involving disjunctive constraints on the dynamics. Simulation of dynamics with disjunctive constraints in this context becomes necessary to estimate, synthesize, and allocate the intended hardware realizable forces in an active suspension. In this paper, we give an algorithm for the previously mentioned problem by solving it as a disjunctive dynamic optimization problem. Based on this, we synthesize and allocate the roll-stabilizing time-dependent active suspension forces in terms of sensor output data. We show that the forces obtained from disjunctive dynamics are comparable with existing force allocations and, hence, are possibly realizable in the existing hardware framework toward enhancing the safety and fault tolerance. Nigam Chandra Parida, Soumyendu Raha, Anand Ramani |
IEEE Trans. Intell. Transp. Syst. | 2 |