In this paper, a stereoview to multiview conversion system, which includes stereo matching and depth image-based rendering (DIBR) hardware designs, is proposed. To achieve an efficient architecture, the proposed stereo matching algorithm simply generates the raw matching costs and aggregates cost based on 1D iterative aggregation schemes. For the DIBR architecture, an inpainting-based method is used to find the most similar patch from the background, according to depth information. The simulation results show that the designed architecture achieves an averaged peak signal-to-noise ratio of 30.2 dB and structure similarity of 0.94 for the tested images. The hardware design for the proposed 2D to 3D conversion system operates at a maximum clock frequency of 160.2 MHz for outputting 1080p (1920 × 1080) video at 60 frames per second.

This paper proposes a splittable amplifier technique that can be either decomposed into two identical halves or merged for enhancing the utilization of the amplifier power and alleviating the memory effect, when applying operational amplifier (opamp) sharing. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one phase simultaneously for use in two circuits. Next, the two small amplifiers can be merged into one amplifier in the other phase for usage in another circuit. Compared with the conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in the split mode. In this paper, three individual sample-and-hold (S/H) circuits with the proposed technique are designed to demonstrate the efficiency of memory effect cancellation. The simulations show that in contrast to the output spectrum of two S/H circuits with conventional opamp sharing, the spurious tones due to the memory effect can be suppressed by at least 14.66 dB in the split mode and at least 7.32 dB in the combination mode with a 0.6-VP-Pinput signal when using the proposed technique.

The high‐efficiency video coding (HEVC) standard for three‐dimensional (3D) video, which is called 3D‐HEVC, improves the compression efficiency for high resolution 3D video sequences. In this study, three coding time reduction algorithms, namely fast coding unit partition, fast prediction unit (PU) partition and search range reduction, are proposed for inter‐prediction of 3D‐HEVC by referring to the depth edge information. The pixels in one object should have the same motion characteristics. By detecting depth edge, we can easily classify the regional pixels if they are in the same object. Thus, in the encoding stage, the sizes of coding and PUs can be determined by the proposed fast coding unit partition and fast PU partition methods, respectively. Furthermore, the range of motion search can be effectively reduced by the proposed search range reduction method. Experimental results show that the proposed depth edge‐based motion search algorithms can reduce the coding time of inter‐prediction by up to 62% on average with negligible quality degradation.

An efficient lossless coding algorithm for encoding residual data based on H.264/AVC that uses the Hadamard transform to take advantage of data compaction is proposed. To reduce redundancies, the transformed coefficients are compacted using a compact truncation. The compacted coefficients are then compressed by an improved context‐based adaptive variable length coding coder. Simulation results show that the proposed lossless residual coding algorithm reduces the bit rate by >7.5% compared with those obtained using existing H.264/AVC lossless coding systems.

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. To simultaneously consider symmetry, wirelength, area utilization, and current/signal paths during analog placement, this paper explores the feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement optimization. Experimental results show that the proposed formulation and algorithms can generate much more compact layouts resulting in similar or even better circuit performance compared with the previous work.

This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm2.

This paper presents an algorithm for implementing the nonlinear-carrier (NLC) control method for a single-phase power factor correction (PFC) rectifier without an input voltage-sensing circuit, an error amplifier in the current shaping loop, or other external control components. Unity power factor and low harmonic distortion are achieved by adapting NLC control with a variable slope ramp. This ramp is created through a slope comparison without any dividers. The proposed method not only achieves a high power factor, but also efficiently simplifies complexity of integrated circuit realization. A 400-W PFC boost rectifier is implemented to verify the performance of the proposed NLC control. The highest power factor reaches to 99.9% with input voltage of 120 V/60 Hz, and the lowest input current harmonic distortion is 4.267%.

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

This paper jointly considers the mechanisms of rate control and the rate-distortion optimization (RDO) for the H.264/AVC hardware encoder. The proposed architecture performs intra prediction and inter prediction with our rate control mechanism in the first two stages. In addition, a low complexity macroblock (MB)-level mean absolute difference (MAD) prediction algorithm which considers both the motion information and the MAD value in the neighboring and current MBs is proposed. The proposed rate control algorithm can reduce the computational complexity and does not suffer from data dependency problems which may decrease the rate-distortion performance, thus it is suitable for H.264/AVC hardware encoders. Furthermore, the RDO-based architecture for the H.264/AVC encoder reduces the number of accurate rate-distortion cost calculators while maintaining the high rate-distortion performance. Experimental results show that the proposed rate control algorithm with the RDO-based architecture can improve the rate-distortion performance of H.264/AVC.

An efficient lossless video codec based on H.264/AVC that uses the Hadamard transform and adaptive truncation (HTAT) method is proposed. Most lossless video coding algorithms avoid transforms in their coding procedures. However, without this transformation, those lossless video coding algorithms cannot take advantage of data compaction. The HTAT method adopts the Hadamard transform to compact data, where the transformed coefficients are adaptively separated into the quotient parts and remainder parts. The quotient parts can be better encoded by entropy coders due to the energy compaction provided by the Hadamard transform. To ensure lossless coding, the remainders are encoded into compact form after exploring the redundancies caused by the Hadamard transform. Simulation results show that the proposed HTAT method has better coding performance than that of the original H.264/AVC lossless coding, with 6.2% and 3.7% reductions in bit rate for all I frame sequences and IPPP sequences, respectively.

This paper presents two low complexity macroblock-level MAD (Mean Absolute Difference) prediction algorithms for H.264/AVC rate control. Both of the algorithms consider the rate-distortion performance and its hardware cost jointly. One of the algorithms predicts the MAD value by observing the motion vector of the surrounding macroblocks (MB), the other one uses numerical analysis to find the best fit weighting factors for the MAD value. These algorithms do not suffer from the MB-pipeline problems which decrease the rate-distortion performance, thus they are suitable for H.264/AVC hardware encoders. Experimental results show that the proposed MAD prediction algorithm can further improve the rate-distortion performance for the rate control scheme. Compared with the JVT-G012 rate control scheme, our algorithms can increase the PSNR to 0.38 dB and 0.35 dB, respectively.

This paper presents a low-complexity rate control (RC) framework for H.264/advanced video coding (AVC) encoders on embedded systems. We consider not only the rate-distortion performance but also its implementation complexity using an efficient hardware/software codesign. The proposed cost-effective macroblock level RC module works in hardware, and the frame-level RC is executed on the system CPU as software. It is less complex than the RC module adopted by H.264/AVC JM reference software, making it more suitable for embedded systems. Experiment results show that the proposed RC outperforms H.264/AVC JM, and the hardware implementation cost is low for an H.264/AVC video encoder.

In this paper, an efficient mode decision algorithm and a high throughput hardware architecture with eight-pixel parallelism for improving the H.264/advanced video coding intra coding efficiency are proposed. Based on the inherent features of the discrete cosine transform, the input block is first transformed and then analyzed to determine its texture directional tendency. A few candidate modes are chosen for cost calculation, which adopts the error model in the sum of absolute integer-transformed differences (SAITD). Experimental results show that the proposed intra prediction algorithm has lower peak signal-to-noise ratio degradation and bit-rate increment compared to other recent designs. Using the SAITD technique, the proposed mode decision algorithm is effectively integrated into intra prediction rather than being a preprocessing unit. For hardware implementation, the proposed intra prediction algorithm in the macroblock level is implemented for prediction computation, mode decision, and reconstruction loop units. The synthesis results show that the proposed architecture can achieve a 100 MHz operation frequency, allowing it to easily support the real-time requirements for video resolutions of up to the 16 source input format.

The lossy video coding is a key technology to compress the video to become very low bit rate data and H.264/AVC standard performs very well in lossy coding. However, the lossless image and video coding still plays an important role, especially in medical applications. Hence, the lossless coding in use of H.264/AVC gains a lot of attentions. In this paper, we introduce simplified interpolations to replace the sample-by-sample DPCM concept, which uses the nearer pixel as the prediction for certain modes to achieve better coding efficiency. The proposed predictions are applied to all intra prediction modes suggested in H.264/AVC. Moreover, the luma/chroma dc blocks reduction can also reduce the syntax elements for entropy coding. With these proposed algorithms, the compression performance of the H.264/AVC lossless intra coding is greatly improved.

A one-cycle control based constant frequency operating trailing-edge continuous conduction mode (CCM) boost type power factor correction (PFC) IC with instant-switch-current control is proposed. By using a level shift circuit, this PFC controller can be operated using unipolar supply voltage. Moreover, the functions of leading edge blanking (LEB) and over voltage protection (OVP) are integrated into the proposed IC to improve its performance.

In this paper, a partial cost intra prediction algorithm based on transform-domain property is proposed. After transform processing, the intensity of the whole block is collected into the first few pixels. The differences in the low frequency region are adopted to represent the total distortion of one 4times4 block. In comparison to the previous fast mode decision algorithms, which mainly reduce the number of candidates in the RDO process, the proposed algorithm simplifies the computation in the cost function. Moreover, the integer transform with cosine multiplication is applied in the proposed algorithm and gets better results in intensity collection. With the benefit of linear transform, the number of operations is further reduced approximately by 40% of the original cost calculation suggested in H.264 JM standard.

This paper proposes a novel scheme of self-timed charge recycling search-line (SL) drivers for content-addressable memories. In the conventional charge recycling SL driving scheme [11], an additional clock needs to be generated from the system clock with stringent requirements for phase and pulse width to control the charge sharing course. In contrast, the proposed scheme can self-sense the end of the charge sharing. Besides, by entering the high-resistant driving state in advance, the proposed scheme reduces the delay overhead of the control logic from 8 to 6 gates delay. Simulation is carried out in a 0.35-µm 3.3-V CMOS process, and the results show the proposed SL driver with load of 512 bits TCAM cells achieves 31.6 fJ/bit/search energy index and 1.19 ns delay time. The achievement illustrates 27.4% energy reduction over buffered driver and 22.2% delay time reduction over the conventional charge recycling SL driver.

In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4times4 inverse integer transform, the 4times4 inverse Hadamard transform and the 2times2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1 k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.

In this paper, we propose an approximate square criterion for H.264/AVC intra mode decision. The sum of square difference (SSD) criterion achieves the best video quality but takes much high computation due to the square operation. A sum of approximate square difference (SASD) criterion is proposed to maintain the video quality and reduce the computation. By applying the characteristic of the SSD criterion, simulation results show the rate-distortion performance of the SASD criterion is close to that of the SSD method. For the hardware implementation, synthesized results show that the proposed approximate square operation respectively reduces 75% and 61% in the area cost and timing delay than that of the square function.

To improve video quality in TV display, we propose an architecture including frame rate up-conversion (FRUC), spatial scaling, and adaptively edge sharpening. The technique of motion compensation is applied both to frame interpolation and to edge sharpening in order to improve visual quality. In conventional methods, the bi-directional motion estimation (ME) is usually employed between two successive frames to interpolate a new frame. The proposed method not only considers temporal correlation, but also exploits the spatial correlation to determine the covered and uncovered region. The weighting of edge sharpness is determined by the magnitude of motion vector (MV) and mean absolute difference (MAD) of the current block to improve image quality. We implement and verify our architecture on a virtual platform with system level design flow. Simulation results show that our method has better PSNR and image quality.

A low complexity fast mode decision algorithm for H.264/AVC intra prediction that uses discrete cross differences (DCD) to reduce the unlikely candidate modes in the RDO calculation is proposed. By using horizontal and vertical differences in different locations, the directions of the edges can be precisely detected. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 56%, with negligible loss of video quality. To realize the proposed algorithm, a VLSI design, which is comprised of a cross difference unit and direction detection unit, is implemented for the mode pre-selection stage of intra prediction. The design is synthesized using UMC 0.18 mum CMOS technology and simulated with Verilog-XL. The operating frequency of the synthesized core can exceed 50 MHz.

In this paper, an efficient algorithm is proposed to improve the decoding efficiency of the context-based adaptive variable length coding (CAVLC) procedure. Due to the data dependency among symbols in the decoding flow, the CAVLC decoder requires large computation time, which dominates the overall decoder system performance. To expedite its decoding speed, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, a low power combined LUT and single output buffer have been adopted to reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard. The maximum frequency can be larger than 210 MHz, which can easily support the real-time requirement for resolutions higher than the HD1080 format.

A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word$\times\,$144-bit ternary CAM, based on a 0.13-$\mu$m 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2% energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.

In this paper, we design a novel architecture for computing all transforms required in H.264/AVC high profile decoder. This flexible architecture design can compute all transforms including 8 and 4-point integer transforms as well as 4 and 2-point Hardamard transforms such that we can reduce the implementation chip area dramatically. With 8 pixels/cycle throughput, this proposed design can complete the computation in 95 clock cycles with 8times8 inverse transform involved or 54 clock cycles without 8times8 inverse transform for one macroblock. Simulation results show that the implemented area is 18.5 k gate counts, and the maximum clock frequency is 125 MHz. For the real-time requirement, the architecture can deal with all existed frame sizes in 4:2:0 format. For example, if this architecture is operated at 106 MHz, it achieves 4096times2304@30 frames/sec.

In this paper, we propose a real time hardware architecture with low cost for histogram difference calculator to process and low-level extraction in our video abstraction system. The highlights are extracted from video data by directly combining simple visual and audio features of video data without specific domain knowledge and hence its low complexity makes it suitable to be implemented in embedded systems. Experimental results show that the condensed skimming clips comprise the interesting and informative parts and most meaningful semantic contents are extracted efficiently

This paper proposes combined decoding architecture and high-throughput flexible transform design to effectively decode the residual data for H.264/AVC decoders. The inverse quantization (IQ) procedure is combined with context-based adaptive variable length coding (CAVL) decoder to efficiently achieve the simplification. Besides, the flexible transform architecture is also proposed for effective computation of all transforms needed in H.264/AVC decoders. Since all the transforms are realized in the same architecture, the flexible transform design with the throughput of 8 pixels/sec needs fewer logic gate counts. Simulation results show that the implemented gate count is 18.6k and the maximum operating frequency is 125 MHz. For real-time requirements, this proposed design achieves 4VGA (1280times960)@30 frames/sec in the worst case.

An improved histogram testing method for analog-to-digital converters (ADCs) is proposed. The proposed method reveals not only the static performance but also the dynamic ones, such as the effective number of bits (ENOB) with a sinusoidal input signal. Therefore, single histogram testing is performed rather than using both the histogram and spectral methods to reduce the total test cost. The proposed testing method was experimentally validated on a commercial 8-bit ADC to demonstrate it effectiveness. The experimental result indicated that the proposed histogram-based test method exhibits a good agreement to the measured results of the classical FFT-based method

In this paper, a low power architecture for realizing the CAVLC decoder is proposed. In traditional VLC decoding algorithms, we could search a level in Huffman coding tree per operation. Therefore, the throughput rate is limited by the searching level. The CAVLC algorithm takes the advantage of the trend among AC coefficients in each block to predict the next codeword. The prediction mechanism can significantly improve the decoding efficiency. Hence, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the power consumption in decoding the VLC codes. The proposed low-power CAVLD architecture achieves the real-time requirement for 720p HD (1280/spl times/720) format, while the clock is operated at 125 MHz. In simulations, the proposed architecture can reduce about 25% of power consumption in comparison to its counterpart without low power design.

In this paper, an efficient in-loop deblocking filter architecture for H.264 video coding system is proposed. The deblocking filter usually need perform both vertical and horizontal directions. A novel data arrangement, called the group-of-pixel (GOP), is designed to efficiently arrange the pixel data stored in on-chip memory. With the proposed GOP arrangement, we do not need the transpose memory, which often occupies excessive chip area, to transpose the direction of the pixel data filtering. Furthermore, the number of total cycles required for GOP-based deblocking filter is reduced significantly. The proposed in-loop GOP-based deblocking filter architecture synthesized with UMC 0.18 /spl mu/m technology could process real-time video in 720p HD (1280/spl times/720) format operated at 100 MHz.

A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word-144-bit ternary CAM, using 0.13-?m 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme.

This paper presents a discrete-cosine transform (DCT)-based adaptive thresholding algorithm to achieve an effective binarization of video image for binary motion estimation (BME). The BME through the full search mechanism requires extremely low hardware complexity. Experimental results show that the proposed adaptive BME attains performance close to the 8-bit resolution ME for low motion sequences with full search strategy. Compared to the well-known single-layer BME, the proposed adaptive algorithm shows better peak signal-to-noise ratio performance and more robustness to complex images. Moreover, the proposed algorithm has a lower computational complexity that is suitable for VLSI implementation with a smaller hardware overhead.

In this paper, a built-in self-test (BIST) methodology used to test the important transmission parameters, signal-to-noise-and-distortion (SNDR) and effective number of bits (ENOB), of analog-to-digital converters (ADCs) is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce high frequency analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. Unlike conventional test methods which compute these parameters based on the spectrum information after fast Fourier transformation (FFT), the presented BIST scheme can directly determine the noise-and-distortion power density and SNDR in time domain. It can reduce the high cost of implementing FFT and windowing functional blocks, and alleviate the difficulty in setting the test frequencies and measurement conditions.

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 µm process parameters, the results show that INL < ±04 LSB and DNL < ±01 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

In this paper, an adaptive postprocessor figured with discrete cosine transform (DCT)-based block classification to effectively remove the so-called blocky effect from compressed video sequences is proposed. The proposed DCT-based detection algorithms for both intraframes and interframes require much lower computation complexity than the spatial-domain approaches. In order to preserve the edge information, the adaptive postprocessor is also designed with a DCT-based edge detection mechanism such that a one-dimensional median filter can be adaptively adjusted to match with the edge orientation. Simulation results show that the proposed DCT-based detection algorithms accurately classifies smooth, edge, or nonsmooth blocks to help the adaptive postprocessor to effectively remove the blocky effect and sharply preserve the edge information.

In this paper, a novel fuzzy logic controller called linguistic-hedge fuzzy logic controller in a mixed-signal circuit design is discussed. The linguistic-hedge fuzzy logic controller has the following advantages: 1) it needs only three simple-shape membership functions for characterizing each variable prior to the linguistic-hedge modifications; 2) it is sufficient to adopt nine rules for inference; 3) the rules are developed intuitively without heavy dependence on the endeavors of experts; 4) it performs better than conventional fuzzy logic controllers; and 5) it can be realized with a lower design complexity and a smaller hardware overhead as compared with the controllers that required more than nine rules. In this implementation, a current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. This design was fabricated with a TSMC 0.35 /spl mu/m single-polysilicon-quadruple-metal CMOS process. In this chip, the LHFLC processes two input variables and one output variable. Each variable is specified using three membership functions. Nine inference rules, scheduled in a rule table with a dimension of 3 /spl times/ 3, define the relationship implications between these three variables. Under a supply voltage of 3.3 V, the measurement results show that the measured control surface and the control goal are consistent. The speed of inference operation goes up to 0.5M FLIPS that is fast enough for the control application of the cart-pole balance system. The cart-pole balance system experimental results show that this chip works with nine inference rules. Furthermore, by performing some off-chip modifications, such as shifting and scaling on the input signals and output signal of this design, according to the specifications defined by the controlled plants, this design is suitable for many control applications.

In this paper, we propose a novel fuzzy logic controller, called linguistic hedge fuzzy logic controller, to simplify the membership function constructions and the rule developments. The design methodology of linguistic hedge fuzzy logic controller is a hybrid model based on the concepts of the linguistic hedges and the genetic algorithms. The linguistic hedge operators are used to adjust the shape of the system membership functions dynamically, and ran speed up the control result to fit the system demand. The genetic algorithms are adopted to search the optimal linguistic hedge combination in the linguistic hedge module, According to the proposed methodology, the linguistic hedge fuzzy logic controller has the following advantages: 1) it needs only the simple-shape membership functions rather than the carefully designed ones for characterizing the related variables; 2) it is sufficient to adopt a fewer number of rules for inference; 3) the rules are developed intuitionally without heavily depending on the endeavor of experts; 4) the linguistic hedge module associated with the genetic algorithm enables it to be adaptive; 5) it performs better than the conventional fuzzy logic controllers do; and 6) it can be realized with low design complexity and small hardware overhead. Furthermore, the proposed approach has been applied to design three well-known nonlinear systems. The simulation and experimental results demonstrate the effectiveness of this design.

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test.

In this paper, we propose transform-domain algorithms to effectively classify the characteristics of blocks and estimate the strength of the blocky effect. The transform-domain algorithms require much lower computational complexity and much less memory than the spatial ones. Along with the estimated blocky strength, we also propose an adaptive finite impulse response (FIR) filter to effectively remove the blocky effect. Simulation results show that the proposed algorithms sharply preserve the edge information and greatly improve the decoded image quality.

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.

In this paper, a tree-based approach is proposed to design the fuzzy logic controller. Based on the proposed methodology, the fuzzy logic controller has the following merits: the fuzzy control rule can be extracted automatically from the input-output data of the system and the extraction process can be done in one-pass; owing to the fuzzy tree inference structure, the search spaces of the fuzzy inference process are largely reduced; the operation of the inference process can be simplified as a one-dimensional matrix operation because of the fuzzy tree approach; and the controller has regular and modular properties, so it is easy to be implemented by hardware. Furthermore, the proposed fuzzy tree approach has been applied to design the color reproduction system for verifying the proposed methodology. The color reproduction system is mainly used to obtain a color image through the printer that is identical to the original one. In addition to the software simulation, an FPGA is used to implement the prototype hardware system for real-time application. Experimental results show that the effect of color correction is quite good and that the prototype hardware system can operate correctly under the condition of 30 MHz clock rate.

The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color documents, we develop a hardware processing module, which realizes the operation of a higher order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.

The 16/9 widescreen TV is becoming popular in the marketplace; however, its aspect ratio is not compatible with the conventional 4/3 SDTV program. We propose a nonuniform conversion to efficiently display 4/3 SDTV programs on a 16/9 high-definition television (HDTV) monitor, for real time HDTV receivers, a parallel video converter is also proposed using nonuniform interpolation. To trade off complexity and performance, we only use one field-memory and one line-buffer for motion adaptation to interpolate the pixels, which can be finished by the parallel computation kernel in one clock cycle. In order to combine parallel computation, the memory-slice method is employed, which is efficiently controlled by a state machine for nonuniform interpolation. With parallel conversion, a high-speed video converter can be achieved for advanced HDTV receivers.

In-this paper, we present an efficient and accurate I/sub DDQ/ fault modeling technique for digital CMOS circuit. Both the normal and faulty "current" behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is obtained. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

We propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by Yang, Bel, and Hisa (see ibid., vol.5, no.1, p.25-30, 1995). Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in a progressive transform mode. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes.>

In this paper, a practical design for built-in current sensors (BICS's) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard.>

This paper presents an array based structure for the fuzzy inference mechanism which is implemented by current-mode circuits. Since the computations of the fuzzy relation and fuzzy inference are in parallel, the inference speed is high and the inference structure is suitable for real-time processing.>

The layout compaction problem with performance consideration is studied. In our approach, the delay upper-bound on the timing critical paths is reduced first, then the layout size is minimized without increasing that delay bound. Either step is formulated as a linear programming problem, and we propose a graph-based simplex algorithm, which replaces most of the matrix operations with graph operations, to solve the problem. Both theoretical analysis and experimental results show that this algorithm is quite efficient.

A complete system which takes the test generation algorithm, the scan cell selection strategy and the structure of the scan chain into account is proposed. It is totally different from the traditional approaches which try to enhance the ability of the individual subject. The goal of this research is to reduce the extra costs caused by the scan design, especially the test application time. Experimental results show that the overall consideration of scan design and test generation can speed up test generation and greatly reduce the amount of test application time.>