Samvel K. Shoukourian

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16ranked-venue papers

3as first author

1since 2021 · last 2025

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 13 · 3 first-author · 1 since 2021Theory of computation · 3Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation › hardware verification and test fault detection	0.5	2	2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation hardware verification and test	0.5	2	2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test memory testing	0.5	2	2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test › design for testability built-in self-test	0.4	1	2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation › hardware verification and test › memory testing march test algorithm	0.1	1	2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

test algorithm template · 0.4fault periodicity table · 0.4test algorithm generation · 0.1fault classification · 0.1

Year	Publication	Venue	Position
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	58
2020	Polynomial algorithm for equivalence problem of deterministic multitape finite automata Hayk A. Grigoryan, Samvel K. Shoukourian	Theor. Comput. Sci.	2
2019	Memory FIT Rate Mitigation Technique for Automotive SoCs abstract This paper considers the reliability and safety issues in automotive applications which are of highest importance. FIT rate is one of the most common metrics used for quantitatively evaluating such issues. Strict requirements exist for acceptable FIT Rate in automotive applications. The problem of calculating the FIT rate at SoC level is considered in this paper and then it focuses on memories, which comprise a large part of current SoCs and have a great impact on the overall FIT rate. The vulnerability factors are considered, which help to get a better approximation of real-life situations. A methodology is presented for mitigating the effects of soft errors in memories via selective adoption of error detecting and correcting codes (ECC). Ways to calculate the FIT rate in the presence of ECC are considered and an advanced ECC solution is presented. Since using ECC increases the SoC area (extra logic and memory bits are needed) and decreases performance (delay in ECC logic that calculates / verifies the codes), a planning solution for choosing which memories should have ECC for optimal reliability/area is presented. Some experimental results are adduced to illustrate the effectiveness of the proposed techniques. Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Yervant Zorian	ITC	7
2019	Armenia: Communicating to World Community in Electronic Test and Design abstract During its 4000 years old history, Armenia was situated at a cultural, historical, and religious intersection and located at the crossroads between Europe and Asia. Today, it is located in the southern Caucasus between the Black and Caspian Seas, bordered on the north and east by Georgia and Azerbaijan, and on the south and west by Iran and Turkey. Armenia has a strong cultural and scientific heritage for thousands of years. It was the first state to adopt Christianity as a state religion, in 301 AD. The Ararat Valley of Armenia is believed to be inhabited since the Stone Age, making it is one of the oldest settled regions in the world. Samvel K. Shoukourian, Yuri Shoukouryan, Vladimir Sahakyan	ITC	1
2019	Innovative Practices on In-System Test and Reliability of Memories abstract This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs. S. Bandyopadhyay, J. Mekkoth, Marc Hutner, Hayk T. Grigoryan, Samvel K. Shoukourian, Grigor Tshagharyan, Yervant Zorian, Gabriele Boschi, Duccio Lazzarotti, Donato Luongo, Hanna Shaheen, Gurgen Harutunyan	VTS	6
2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism abstract This paper introduces a novel solution for building fault aware memory built-in self-test infrastructure based on rules of fault periodicity and regularity in memories and test algorithms. These periodicity and regularity rules are described via special internal structures named fault periodicity table (FPT) and test algorithm template (TAT). Three dimensions of evolution are considered as inputs for forming the mentioned structures: memory cells, multidimensional memory circuits, and memory systems for systems-on-chip where memories are distributed in different subchips. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. FPT allows considering any large number of faults in one table while TAT allows constructing test algorithms without using test algorithm generation tools. Experimental results of the solution applied to both Planar-based (90/65/45/28 nm) and FinFET-based (16/10/7 nm) memory technologies are adduced also in this paper. Gurgen Harutunyan, Samvel K. Shoukourian, Yervant Zorian	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2
2018	Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs abstract Automotive innovation is driving the need for built-in reliability, safety and security solutions and architectural design to mitigate emerging threats and, particularly, the number of possible sources affecting arisen failures. In other words, the problem can be stated as reduction of failure rate-one of the most common metrics used for reliability evaluation. Soft errors in memories will be considered in the paper. Their FIT rate is significantly more than the typical FIT rate for a hard reliability failure. A special technique is described to assess the soft error rate and to mitigate the effects of soft errors via error correcting codes (ECC). Ways to calculate the failure rate in the presence of ECC are considered jointly with different ECC solutions. Since ECC also incurs a significant area overhead, a problem arises how to choose memories in SoC which should have ECC in order to meet the reliability requirements and, at the same time, the area constraints. In this paper, an efficient ECC planning solution is presented to solve the problem. The experimental results are adduced which show the advantages of the proposed solution. Hayk T. Grigoryan, Samvel K. Shoukourian, Gurgen Harutunyan, Yervant Zorian, Costas Argyrides	ITC	2
2013	An effective solution for building memory BIST infrastructure based on fault periodicity abstract This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	VTS	2
2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs abstract In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2
2011	A Robust Solution for Embedded Memory Test and Repair abstract This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys Design Ware allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed. K. Darbinyan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	Asian Test Symposium	3
2011	Generic BIST architecture for testing of content addressable memories abstract Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns. Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IOLTS	3
2011	Symmetry Measure for Memory Test and Its Application in BIST Optimization Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	J. Electron. Test.	3
2010	The Equivalence Problem of Deterministic Multitape Finite Automata: A New Proof of Solvability Using a Multidimensional Tape Alexander A. Letichevsky, Arsen S. Shoukourian, Samvel K. Shoukourian	LATA	3
2008	The equivalence problem of multidimensional multitape automata Haik Grigorian, Samvel K. Shoukourian	J. Comput. Syst. Sci.	2
2004	A Methodology for Design and Evaluation of Redundancy Allocation Algorithms abstract A methodology for design and evaluation of redundancy allocation algorithms based on prime algorithms is proposed for memory devices with spare elements. The methodology can be applied to any memory device with spare elements. It allows the design of simple but effective built-in redundancy allocation (BIRA) algorithms working "on-the-fly" with BIST. The methodology allows also reasonable trade-off between repair coverage and hardware/time complexity during the implementation. A basic toolset for design and evaluation of BIRA algorithms based on the proposed methodology is developed and preliminary results of experiments on the application of the tool for self-test and repair (STAR) type SRAM memories are adduced. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	VTS	1
1995	An approach for system tests design and its application abstract An approach for system test design is suggested and justified by the corresponding mathematical model. It is based on the representation of a testing process in an aggregate form of two dynamically interacting components: a control testing table and a testing processor. Control testing tables are equivalent to linear programs which process Boolean arrays. It is proved that the correctness problem for such programs is solvable and polynomial complexity algorithm is suggested. The utilization is considered for the approach when designing system tests for multicomputer systems and complexes, designing a software system for microcode synthesis and for performance evaluation of multi-user systems. Samvel K. Shoukourian, Armen G. Kostanian, Valery A. Margarian, Ayman A. Ashour	VTS	1