Demo Data from SIGIR 2026 / reviewers in the wild / expert
Hezi Azatchi
dblp:58/6155
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 96% Parallel and multicore computing · 4% | |
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.1 | 2 | 2006 | A generic micro-architectural test plan approach for microprocessor verification · DAC 2005 Advanced Analysis Techniques for Cross-Product Coverage · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test
coverage analysis |
0.1 | 1 | 2006 | Advanced Analysis Techniques for Cross-Product Coverage · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test
functional verification |
0.1 | 1 | 2006 | Advanced Analysis Techniques for Cross-Product Coverage · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test
hardware verification |
0.1 | 1 | 2006 | Advanced Analysis Techniques for Cross-Product Coverage · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test
processor verification |
0.1 | 1 | 2005 | A generic micro-architectural test plan approach for microprocessor verification · DAC 2005 |
Runtime systems and virtual machines
garbage collection |
0.0 | 1 | 2003 | An on-the-fly mark and sweep garbage collector based on sliding views · OOPSLA 2003 |
Parallel and multicore computing
multiprocessor system |
0.0 | 1 | 2003 | An on-the-fly mark and sweep garbage collector based on sliding views · OOPSLA 2003 |
Methods — techniques the papers use, named apart from their topics
sliding views · 0.1interactive visualization · 0.1coverage model analysis · 0.1systematic partitioning · 0.1design-independent test plan · 0.1mark-and-sweep · 0.0mark and sweep · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Integrating generations with advanced reference counting garbage collectorsabstractAbstract We propose the use of generations with modern reference counting. A reference counting collector is well suited to collect the old generation, containing a large fraction of live objects that are modified infrequently. Such a collector can be combined with a tracing collector to collect the young generation, typically containing a small fraction of live objects. We have designed such a collector appropriate for running on a multiprocessor. As our building blocks, we used the sliding‐views on‐the‐fly collectors. We have implemented the new collector on the Jikes Research Java Virtual Machine (Jikes RVM) and compared it with the concurrent reference counting collector supplied with the Jikes RVM package. Our measurements demonstrate short pause times, retaining those of the original on‐the‐fly collectors and a gain in application throughput time. It turns out that a modern reference counting collector may benefit from the use of generations. Copyright © 2006 John Wiley & Sons, Ltd. Hezi Azatchi, Erez Petrank |
Concurr. Comput. Pract. Exp. | 1 |
| 2006 | Advanced Analysis Techniques for Cross-Product CoverageabstractCoverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools' help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimidating and time-consuming task. This paper presents several techniques for coverage analysis. These techniques range from highly interactive and dynamic analysis that allows users to focus on certain aspects or areas of interest in the coverage model to fully automated coverage analysis, which identifies uncovered or lightly covered areas. The proposed techniques provide additional means for extracting relevant, useful information, thereby improving the quality of the coverage analysis. A number of examples show how the proposed method improved the verification of actual designs Hezi Azatchi, Laurent Fournier, Eitan Marcus, Shmuel Ur, Avi Ziv, Keren Zohar |
IEEE Trans. Computers | 1 |
| 2005 | A generic micro-architectural test plan approach for microprocessor verificationabstractModern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design. Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet |
DAC | 2 |
| 2003 | Integrating Generations with Advanced Reference Counting Garbage Collectors
Hezi Azatchi, Erez Petrank |
CC | 1 |
| 2003 | An on-the-fly mark and sweep garbage collector based on sliding viewsabstractWith concurrent and garbage collected languages like Java and C# becoming popular, the need for a suitable non-intrusive, efficient, and concurrent multiprocessor garbage collector has become acute. We propose a novel mark and sweep on-the-fly algorithm based on the sliding views mechanism of Levanoni and Petrank. We have implemented our collector on the Jikes Java Virtual Machine running on a Netfinity multiprocessor and compared it to the concurrent algorithm and to the stop-the-world collector supplied with Jikes JVM. The maximum pause time that we measured with our benchmarks over all runs was 2ms. In all runs, the pause times were smaller than those of the stop-the-world collector by two orders of magnitude and they were also always shorter than the pauses of the Jikes concurrent collector. Throughput measurements of the new garbage collector show that it outperforms the Jikes concurrent collector by up to 60%. As expected, the stop-the-world does better than the on-the-fly collectors with results showing about 10% difference.On top of being an effective mark and sweep on-the-fly collector standing on its own, our collector may also be used as a backup collector (collecting cyclic data structures) for the Levanoni-Petrank reference counting collector. These two algorithms perfectly fit sharing the same allocator, a similar data structure, and a similar JVM interface. Hezi Azatchi, Yossi Levanoni, Harel Paz, Erez Petrank |
OOPSLA | 1 |