A new subband echo canceler (SBEC) structure is proposed to reduce the transmission delay introduced by conventional SBEC structures, without distorting the near-end signal. The proposed structure is based on computing two output errors, one for using during single-talk and the other one for using during double-talk periods. With the SBEC structure we propose a double-talk detector with a subband configuration which allows a fast and accurate detection of double-talk periods, enabling the SBEC algorithm to track changes in the echo path impulse response when the near-end signal is absent. Computer simulations using actual speech signals, and subjective evaluation tests are given to show the convergence performance, tracking and double-talk detection ability, of the proposed scheme.>

An acoustic echo-canceler for teleconferencing systems is realized based on the frequency bin adaptive filtering (FBAF) algorithm. In the FBAF algorithm, each frequency bin does an independent adaptive filtering, so that parallel processing can be used to increase the throughput of the system. Hardware size can be reduced to about 25% of the FIR time domain adaptive filter (TDAF) requirement. The realized echo canceler allows a comfortable conversation with only 8 ms of delay. The hardware prototype contains 12 VSP chips and one DSP chip, An ERLE (echo return loss enhancement) of 30 dB was achieved using this prototype hardware for an echo reverberation path with 260 ms delay. An efficient method for normalizing the convergence factor of the FBAF algorithm with a correlated input signal is given that speeds up the convergence rate. The performance is shown by computer simulation.>

A subband echo canceler structure (SBEC) is proposed which allows large decimation factors with no degradation due to frequency gaps or aliased components. It also reduces the transmission delay of conventional SBEC, while preventing distortion of the local signal. Also proposed is a double-talk detector which takes advantage of the subband realization form for speed and accuracy. Computer simulations show that it achieves a large echo-return loss enhancement and convergence rates almost independent of the input signal characteristics with transmission delay around 10 ms using decimation factors of 16 or greater.>

A multimode source/channel coder which can dynamically control the balance of source and channel coding according to the channel quality is introduced. As an example of such a system, a 4.8-kb/s code excited linear predictive coder with three coding modes (A, B1, and B2), each of which has different bit assignments to source and channel coding, is presented. The optimum coding mode is selected in each frame, based on an evaluation of the spectral distortion (SN/sub LAR/) in reproduced speech. The threshold value of SN/sub LAR/ for mode decision is varied according to the channel error rate. Computer simulation shows that 2 dB and 3 dB of SNR/sub seg/ improvement is achieved at a bit error rate of 3*10/sup -3/ and 3*10/sup -2/ respectively, over conventional CELP without channel coding.>

A new 8 kbps speech coding algorithm called TC-MQ (time domain compression ADPCM-MQ) is proposed. It is based on time scale modification and sub-band coding with the aid of ADPCM with a multiquantizer. For time scale modification, the decimation/interpolation technique is introduced for the unvoiced period. Furthermore, in order to get computational accuracy of the pitch extraction for the voiced period, a method using the normalized autocovariance function is proposed. The algorithm was confirmed by computer simulations. The segmental SNR was about 13-16 dB for Japanese short sentences. A good mean opinion score value was also obtained by means of a subjective evaluation test.>

This paper describes a complete hardware implementation of a 24 channel transmultiplexer employing a digital signal processor. The algorithm for the TDM-FDM translation adopted here is a modification of the FFT and digital polyphase method. The modification is mainly directed towards the reduction of roundoff noise, so that the wordlength of the processor can be minimized. In this case, 16 bits for multiplication with double precision accumulation is found to be sufficient to meet the noise requirements as recommended by CCITT G.792. The above modification enables the implementation of the translation algorithm by a 16 bit parallel type digital signal processor. This processor is designed to be firmware controllable and, thus, has a wide range of applications. The entire 24 channel transmultiplexer comprises 1) four signal processors, each handling 12 channels one way translation including signaling; 2) digital interface part to connect to 1.544 Mbit/s PCM system; and 3) codec and Nyquist filter to connect to two 12-channel FDM systems.