As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.

We analyze the electrical phenomena that can affect the integrity of the communication among different chips within a System in Package (SiP). We address these issues for a real case, for which electrical parameters are extracted from layout and used to build a netlist employed for electrical characterization. We show that crosstalk, and in particular inductive crosstalk, is the electrical phenomenon mainly affecting signal transmission within the SiP. Then,we evaluate the kinds of errors that can be originated. We show that errors caused by inductive coupling among SiP interconnects can be unidirectional only, thus allowing designers to implement error control coding techniques based on All Unidirectional Error Detecting codes. This allows significant cost reduction over the alternate use of non-unidirectional error detecting codes.