SRAM has become the dominant block in modern ICs and constitutes more than 50% of the die area. The increase of process variations with continued CMOS technology scaling is considered one of the major challenges for SRAM designers. This process variations increase causes the SRAM cells to functionally fail and reduces the chip functional yield considering the static noise margin stability failures (i.e., cell flips when accessed), write failures (i.e., cell is not written within the write window), and read access failures (i.e., incorrect read operation). In this paper, novel negative capacitance circuits are developed, for the first time, to statistically improve the SRAM read access yield under process variations by reducing the bitlines parasitic capacitance. Post layout simulation results, referring to an industrial hardware-calibrated TSMC 65-nm CMOS technology, show that the adoption of the negative capacitance circuit to a 512 SRAM cells column is capable of improving the read access yield from 61.9% to 100%.

An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are demonstrated. This study shows that the proposed A-ABB reduces the standard deviations of the frequency, the dynamic power and the leakage power by factors of 6.6 X, 8.8 X, and 3.3 X, respectively, when both D2D and WID variations are considered. In addition, in this presented case study, initial total yields of 16.8% and 5.2% are improved to 99.9% and 84.1%, respectively. The advantage of the proposed A-ABB is its lower area overhead allowing it to be used at lower granularity level than that of the previously published ABB circuits.

Sub-threshold SRAM cells are attractive because of their low leakage power and low access energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to their low supply voltage, high density, and shrinking geometry. Moreover, the increase in statistical variations in advanced nanometer CMOS technologies poses a major challenge for sub-threshold circuits designers. In this paper, analytical models for the sub-threshold SRAM critical charge variations, which account for both die-to-die (D2D) and within-die (WID) variations, are proposed. The derived models are then compared with Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper also provides novel design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. In addition, it demonstrates that the relative critical charge variability is minimum at a certain temperature value. Then, the circuit designer can employ these results with temperature control techniques to minimize the critical charge variability in the early design cycles, especially, for applications with strict soft error rate (SER) constraints. In Zaddition, the proposed models show that the device sub-threshold swing coefficient can be optimized to minimize the relative critical charge variability.

A direct adaptive body bias (D-ABB) circuit is proposed in this paper. The D-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations, and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The D-ABB circuit consists of threshold voltage estimation circuits and direct control of the body bias performed by on-chip direct controller circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are presented. These results show that the proposed D-ABB reduces the standard deviations of the frequency, the dynamic power, and the leakage power by factors of 5.5×, 6.4×, and 4.5×, respectively, when both D2D and WID variations are considered. In addition, in the presented case study, initial total yields of 16.8% and 13% are improved to 100% and 91.4%, respectively. The proposed D-ABB circuit exhibits lower area overhead compared to the other ABB circuits reported in the literature.

Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compared to Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the critical charge variability. The derived analytical model accounts for the impact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its variability.

In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop (M-C2MOS-MSFF) exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.

Dynamic logic circuits are considered the best choice for high performance applications due to their relatively high speed. These high performance applications have strict timing constraints. Moreover, process variations create a large variability in the dynamic circuit delay in scaled technologies impacting the timing yield. In this paper, the negative capacitance is adopted, for the first time, for statistical timing yield improvement under process variations. Simulation results show that the adoption of the negative capacitance at the output of a 16-input dynamic NOR gate improves the timing yield by reducing the dynamic circuit delay. In addition, the negative capacitance adoption results in power saving of 10% and reduces the delay variability by 57.6%.

Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperature. In this paper, a comparison of the static and dynamic sleep signal generation techniques for SMT processors is presented. This is conducted under various workloads to assess their effectiveness in leakage power management. Results show that the dynamic approach exhibits a threefold increase in leakage savings, compared with that of the static approach for certain functional units.

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.

In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without incurring any physical or performance penalties. The newly developed methodology is applied to several FPGA benchmarks, and an average leakage savings of 50.3% is achieved in a 90-nm CMOS process. Moreover, a modified version of the methodology is implemented to improve the performance of the final design, and again, considerable leakage power savings are achieved. Furthermore, the methodology is extended to find the lowest leakage states for several future predictive Berkeley CMOS technologies.

Power gating techniques are rapidly gaining popularity assisting the management of leakage power consumption for deep submicrometer microprocessors' functional units. Power gating is based on an input sleep signal to set the functional unit into a low leakage mode. However, power gating techniques in general inherently lack information about the utilization profile of the functional units they manage. This limitation is usually handled either statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles or dynamically by changing the number of cycles before the sleep signal is generated depending on the previous history of operation. In this paper, a comparative study between the static and dynamic approaches regarding the power-performance tradeoff will be presented. It will be shown that the dynamic sleep signal generator is capable of tracking the operation of the functional units while achieving accuracies up to 90% compared to an average of 40%-60% for the static sleep signal generator (SSSG). Additionally it saves up to 80% more leakage versus the SSSG. This study is very important in assisting circuit designers choose between both techniques depending on the power gated circuit.

A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.

This paper presents a four-stage CMOS distributed amplifier (DA) design implemented in standard 0.18 mum CMOS technology. The proposed design eliminates the need for transmission line capacitors and, consequently, uses significantly smaller spiral inductors compared with the previous designs. Using the minimum size inductor, the bandwidth of the amplifiers is extended, and the quality factors of the on-chip inductor are improved. Proposed DA occupies the smallest die area (0.3mum*0.8mum) amongst the DAs reported with the same performance. A unity gain bandwidth of 10 GHz and a gain of 15 dB are measured. DC power dissipation is 56 mW

In this work, a new termination technique for the averaging network of the flash analog-to-digital converter (ADC) input pre-amplifiers is devised. The proposed technique allows efficient suppression of pre-amplifiers offset voltage while consuming no over-range voltage headroom. This makes it suitable for deep-submicron technologies. This technique is applied to the design of a 2.5GS/S flash ADC in 0.13mum CMOS technology to estimate the resulting saving in the input capacitance and power dissipation of the pre-amplifier array

This paper presents a novel loss compensation technique, an active negative resistor produced by a capacitively source degenerated configuration, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). This configuration provides the desired isolation from the transmission line at lower frequencies, and a frequency-increasing negative conductance that can fully compensate for the loss of the on-chip inductor over a broad frequency band. A 40 GHZ three-stage 0.13 mum CMOS DA is devised that outperforms previously published CMOS DAs by providing a large gain-bandwidth product of 200 GHz-dB with an improved gain-flatness of plusmn0.2 dB. The proposed loss compensated DA dissipates 24 mW from a 1.2 VDC supply

Leakage power is projected to comprise approximately 50% of the processor's power for sub 65 nm technologies. Much of this power is consumed in the processor's functional units. Accordingly, leakage control techniques are employed to reduce leakage in these functional units. Many of these techniques are dynamic and are based on an input sleep signal to initiate a low leakage mode. However, since most of these leakage control techniques are based on circuit level schemes, such techniques inherently lack information about the operational profile of the functional units they manage. This limitation is usually handled statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles. In this paper, the limitations of the static sleep signal generation approach are identified, and the use of a dynamic alternative that is capable of adopting the counter length to the running application is proposed. In order to assess the accuracy of the proposed dynamic sleep signal generator, the length of the sleep period following the sleep signal generation is used as a metric to identify the usefulness of utilizing the dynamic approach. Experimental results for the dynamic alternative shows up to 98% accuracy in predicting the length of the standby period compared to an average of 40-60% in the static case, which translates into increased leakage savings. This is achieved while consuming 360 muW of overhead power at 1 GHz

In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the block activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.

FPGAs are witnessing a big increase in their applications, especially with the introduction of state-of-the-art FPGAs using nanometer technologies. This has been accompanied with a big increase in power dissipation in FPGAs, which forms a road block to the integration of FPGAs in several hand-held applications. Motivated by the increase in the percentage of leakage power dissipation to the total power dissipation in modern technologies, this work presents a complete CAD flow to mitigate leakage power dissipation in FPGAs. The algorithm is based on a FPGA architecture that employs multi-threshold CMOS technology. The flow is based on the VPR flow and it aims to pack and place logic blocks that exhibit similar idleness close to each other so that they can be turned off during their idle time. The flow is tested with a CMOS 0.13 m dual-vth technology and achieved an average power saving of 22%.

As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPGAs CAD flow to mitigate leakage power dissipation through the use of multi-threshold CMOS technologies to pack and place logic blocks that exhibit similar idleness close to each other so they can be turned off during their idle time. The modifications are integrated into the VPR flow and tested on several FPGA benchmarks using a CMOS 0.13μm dual-Vth technology, resulting in an average leakage power savings of at least 20%

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.

An automated optimization-based design strategy is proposed for single-level MOS Current Mode Logic (MCML) gates to overcome the complexities of the gate design procedure. The proposed design methodology determines the values of the design variables that achieve the minimum power dissipation point while attaining the required performance. The proposed design methodology has the advantage of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on the MCML gate performance is presented. The proposed strategy is used to design two popular circuits, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the gate parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as the technology scales down is investigated.

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.

Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-/spl mu/m CMOS process have shown 2.8 to 9.9/spl times/ in energy savings and 1.02 to 6.36/spl times/ reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32/spl times/64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach.

A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip re-liability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash converter resolution by pre-calculating the most significant bits. 1

This paper presents a rapid and efficient modeling method, based on the microstrip lines theory, for the coupling between a device contact and the substrate backplane. We derive simple closed-form formulas to model spiral inductors as important substrate-noise sources in mixed-signal systems. The model has been verified via IE3D simulations up to 35 GHz, and is adaptable to CAD tools. We demonstrate that the accuracy of the proposed model is better than 8%.

A new contention-free domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 /spl mu/m CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area are also presented.

A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

This paper presents two rapid and yet accurate modeling methods for substrate coupling between a device contact and a substrate backplane. We discuss effects of physical parameters and geometrical characteristics of the contact and the substrate on the proposed models. We also derive model expressions for extraction of circuit-model elements of the substrate. Both methods are efficient for speed, memory usage, and adaptable to computer-aided design (CAD) tools for optimization tasks. The accuracy of both methods, the parametric modeling method and the microstrip line approximation method, is validated by comparing with the rigorous simulation data obtained from IE3D. Using the new models, we record a much higher speedup factor and extremely lower memory requirements compared to other published methods. The modeling methods are extended to two-layer structures and the models are applied to spiral inductors for verification purposes. In our research, we have validated the models over a wide range of frequencies up to 20 GHz.

This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs.

A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division ratio, and hence the phase-detector phase-noise, without the need of multiple loops, when used in conjunction with a DDS, this architecture simplifies the DDS design leading to a low-power architecture. Furthermore, this architecture allows for a large loop bandwidth thus suppressing the VCO phase-noise. The advantages of this architecture are highlighted and system- and circuit-level simulations presented.

CMOS remains the mainstream IC technology and optimization of digital CMOS circuits is a major focus of research. This paper presents a comprehensive model for estimation and optimization of the delay in submicron digital CMOS circuits. Our delay model for a logic gate depends on the topology of the gate, the size and topology of the preceding gate, and the load. This model is explicit in terms of the widths of the transistors and lead to closed-form formulas for optimization of digital CMOS gates. These formulas are simplified and approximated into rules of thumb for quick optimization and obtaining initial guess for running a CAD tool. Delay optimization of a critical path is performed by solving a set of non-linear transistor sizing formulas using iteration. Very good agreement is observed between the model and HSPICE simulations.

A Differentially controlled monolithic LC-VCO along with a differential charge pump are used to implement a differential PLL for substrate noise immunity. The differential VCO control is achieved with minimal increase in the power consumption and without sacrificing the tuning range. In a 0.5 mCMOS technology the measured VCO phase noise is-119dBc @1.0MHz and the tuning range is 26 % of the 1.25GHz center frequency, at a total power consumption of 4.0mA from 3V supply. The common mode rejection of the VCO control lines is more than 2000 at DC. The new differential charge pump architecture provides common mode correction without the need for a clean reference.

A new approach to modeling the decoding hierarchy in a hierarchical word line (HWL) SRAM architecture using integer-linear programming (ILP) is introduced. Using this approach, the HWL architecture is shown to be inadequate for very large SRAM sizes. Alternatively, a new low-power high-speed SRAM architecture is described. This architecture is shown to have fairly constant speed and power dissipation for sizes ranging between 32 kb to 4 Mb. Low-power is achieved by a voltage boosting technique not requiring a two-step voltage and by a new method of tristating memory cells during a write operation. The SRAM was implemented in a 0.35 /spl mu/m CMOS technology operated at 150 MHz while dissipating only 10 mW.

This paper presents a simple, yet efficient method to characterize the effective capacitance in data-path macros for architectural-level power estimation. Given a library of hard-macros, a capacitance model based on linear regression is derived for each macro. A transistor-level tool is employed for capacitance extraction. The capacitance models can be used during architectural-level power estimation. Unlike previous approaches, our characterization methodology assumes no specific word-level statistics of the input data, requires little knowledge about the structure of the modules, allows the user to trade-off accuracy and characterization time, and propagates effective capacitance directly from transistor-level (real) implementations. Simulation experiments on a set of data-path components with various sizes are performed. Compared to a previously published approach, our scheme significantly improves the accuracy of RTL power estimation and produces results within 15% from a transistor-level tool on the average.

Unlike most research involving finite field multipliers, this work targets a low-power multiplier through the application of various power reduction techniques to different types of multipliers and comparing their power consumption among other factors, rather than comparing complexity measures such as gate count or area. Gate count is used as a starting point to choose potential architectures, namely, polynomial and normal basis architectures. Power reduction techniques employed are mainly concerned with architecture- and logic-level low-power techniques. They include supply voltage reduction, power cost estimations, using low-power logic families and pipelining.

Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions.

The C-element is one of the most frequently used primitives in asynchronous control circuits. This paper introduces various single-rail and double-rail implementations of the C-element, explains ways to optimize their performance and compares them with respect to energy and speed in a micropipeline control circuit environment. The issue of divergence of the complementary outputs in the double-rail implementations is also discussed.

Several high-level low-power design techniques have been incorporated in the design of a decimation filter for software radio.These include; operation minimization, multiplier elimination and block deactivation.Analysis and simulation results indicate that these techniques can achieve a 4 times reduction in power dissipation.An interleaved multiplier-accumulator array is used in the lowpass filter.The decimation filter designed has a programmable resolution, that varies from 12 to 20 bits.The entire decimation filter has been designedin a 3.3 Volt O.~/.UZZ CMOS technology.-. -..

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C/sup 2/PL) is presented. Some types of 3-2 compressors in C/sup 2/PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the C/sup 2/PL compressors have the best performance in power, delay and number of transistors.

The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms.

This paper describes a video compression algorithm that has a reduced computational complexity. The subband video compression algorithm uses a simplified analysis/synthesis filter bank and a vector quantization coding algorithm. The use of the simplified analysis/synthesis filter banks reduces the power dissipation by 23 times over other algorithms at the expense of a 4 dB reduction in the signal to noise ratio. The vector quantization algorithm is a computational algorithm instead of the power consuming memory lookup algorithms.

One of the most frequently used primitives in asynchronous control circuits is the C-element. The three most popular CMOS implementations of the C-element are compared with respect to energy-efficiency, delay, and area, with an emphasis on energy. The three implementations have been introduced by Sutherland, Martin, and Van Berkel. We show that in a typical environment, Van Berkel's implementation is superior to the other implementations with respect to energy consumption and area, for the same delay.

A novel 32-bit adder has been designed using a Conditional Sum Adder (CSA) architecture and CPL-like logic implementation. The new implementation outperforms several architectures such as CLA, CS and Manchester which use the CMOS circuit styles (CPL, DPL, TG, static-conventional) in terms of power and speed. This is verified for a range of power supply voltage from 3.3 V down to 1 V. The comparison is carried out for two designs, minimum size and optimized speed.

In this paper, a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits is introduced. The model is based on Berkeley Short-Channel (BSIM) model and fits HSPICE simulation results well. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented.

A new software tool TRASIM (Two-Dimensional Transient Simulator) has been developed for arbitrary, planar semiconductor devices. A finite difference technique is employed with a modified, decoupled Gummel-like method. The memory requirements are reduced significantly compared to the conventionally used Newton-like methods. TRASIM exhibits a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and efficiency make the method attractive for the future 3-D applications. The software uses the drift-diffusion model, with up-to-date mobility and lifetime models. External RC-chains may be connected to device electrodes. Numerical examples are presented illustrating the advantages of the modified Gummel method over the Newton method, for transient simulation.>

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.>

The performance of the different two-level series-gated CML BiCMOS schemes has been studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, have shown an improvement of 42% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating an the low power regime (>

A speech recognition system is developed utilising multi-layer perceptrons (MLPs) as speech-frame predictors. A Markov chain is used to control changes in the MLP's weight parameters. Analytical results and speech recognition experiments indicate that when joint (nonlinear/linear) prediction is performed within the hidden layer of the MLP, the model is better at capturing long-term data correlations which improves speech recognition performance. A discriminative training technique based on the maximum mutual information criterion is presented for training this class of models. The performance of the system on vowel classification tasks when trained with this method is shown to be superior to the same system trained using the maximum likelihood training criterion.>

In this paper, a new all-N-logic high speed pipelined single-phase dynamic CMOS logic is introduced and analysed. The use of an all-N-logic allows the speed of the proposed circuits to be 2-3 times the speed of conventional CMOS dynamic circuits. The operating speed of the proposed pipelined circuits is simulated using 0.8 /spl mu/m CMOS technology and reaches as high as 890 MHz. The pipelined 8-b carry generator of 5-stacked NMOS's which operates at a clock rate of over 550 MHz has been simulated.>

A new active-pull-down non-threshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an APD-NMOS emitter-follower stage. Simulation results based on 0.6-/spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 3.4/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV. A comparison of critical-path delay has showed the superiority of the novel circuit over ECL circuits especially in the low-power region.>

A methodology for automated synthesis of mixed analog/digital hardware architectures for Artificial Neural Network (ANN) applications is presented, The ANN system is input in the form of a Data Flow Graph (DFG) of operators. The output is a high-level interconnection description of mixed analog/digital building block circuits that is generated by searching a multidimensional design space to satisfy the throughput requirements and minimize an area-time cost function. A combination of quantitative analysis and behavioral modeling techniques tackles the problems of hardware nonidealities by screening suitable analog circuits. Digital hardware is employed when no analog circuit is found that satisfies the performance requirements of any operation. A heuristic partitioning scheme reduces the interfaces between blocks of circuits operating in analog and digital modes. The parallelism in ANN systems is, handled by a new scheduling and allocating procedure that selectively sequentializes groups of operations with the goal of iteratively improving an area-time cost function. The synthesizer is also capable of embedding hardware units that are intended to operate asynchronously. The synthesis methodology is illustrated with two design examples.>

A relaxed linear programming model which simultaneously schedules and allocates functional units and registers is presented for synthesizing cost-constrained globally optimal architectures. This approach is important for industrial applications, because it provides exploration of optimal synthesized architectures and early architectural decisions have the greatest impact on the final design. An integer programming formulation of the architectural synthesis problem is transformed into the mode packing problem. Polyhedral theory is used to formulate constraints that decrease the size of the search space, thus improving solution efficiency. Execution times are an order of magnitude faster than for previous heuristic techniques. The present approach breaks new ground by (1) simultaneously scheduling and allocating in practical execution times, (2) guaranteeing globally optimal solutions for a specific objective function, and (3) providing a polynomial run-time algorithm for solving some instances of this NP-complete problem.>

BiCMOS technology is one of the leading candidate technologies for VLSI circuits. The authors provide here the results of a simulation-based characterization study of different BiCMOS logic circuits. Different techniques for testing BiCMOS logic circuits are studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is introduced.>

STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits that conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solve unit that dynamically integrates analytical model equations across hierarchical boundaries. The output of the solver is a flattened homogeneous model that is customized to a user-specified topology and set of performance specifications. The output is thus tailored for optimization and other numerically intense design exploration procedures. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via a successive solution refinement methodology. Multilevel models of increasing sophistication are used by scan and optimization modules to converge to what is likely a globally optimal solution. Design experiments have shown that STAIC can produce satisfactory results.>

One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and busses, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing optimal schedules which minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high performance architectures. A partially structured tight IP formulation of the architectural synthesis problem provides globally optimal schedules for peicewise linear cost functions, using branch and bound, in execution times faster than previous research. This research breaks new ground by 1. simultaneously scheduling and allocating hardware resources including interconnect, 2. support for asynchronous and analog interfaces, and 3. guaranteeing globally optimal solutions in practical execution times.

A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Some integral facets of this polytope were extracted and generalized to produce integral solutions using the simplex algorithm without the need to branch and bound. Execution times are faster by an order of magnitude than previous research which makes use of heuristic techniques. This research breaks ground by simultaneously scheduling and allocating with practical execution times; guaranteeing globally optimal solutions for a specific objective function; and providing a polynomial runtime algorithm for solving this NP-complete problem.>

The authors propose a learning technique for the multilayer perceptron based on an error function which is linear in the output layer weights, allowing for optimal adaptation of these weights. The weight adaptation sequence was modified to take full advantage of the proposed learning method. The application of the technique to parity problems indicates a drastic improvement in the convergence time compared to the conventional backpropagation technique. The number of iterations needed for convergence by the technique was about 10% of that needed by conventional backpropagation. This result makes the technique a more attractive alternative for real-time nonlinear adaptive filtering tasks. A perceptron using this method can be a very strong candidate for common nonlinear filters, with the advantage that the nonlinearity in the perceptron structure is not restricted as in such filters

Existing interfaces for high-level synthesis dictate that the synthesis process be iterative rather than interactive. This paper presents an interface tool for architectural synthesis that introduces real-time interaction to high-level synthesis interfaces. ACE makes innovations in the dynamic display of synthesizer transformations and introduces new concepts in input algorithm specification.

A design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units, and parallellism of the architecture are all explored in the design space. The synthesized architecture is a multibus multifunction unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably with other synthesis techniques.>

An architectural synthesis methodology for a multibus multifunctional unit processor is presented. It is implemented as part of a design aid tool called SPAID. The input to SPAID is a DSP flow graph algorithm description with the required throughput and latency. The synthesized processor is a self-timed element externally, while it is internally synchronous and suitable for a systolic multiprocessor implementation for large DSP applications. For a benchmark elliptic filter algorithm SPAID synthesizes architectures with a linear topology that use fewer interconnects and multiplexers than other systems synthesizing random-topology architectures for the same throughput.>

An integrated design and test synthesis methodology is presented with area, delay, and test cost constraints. This methodology, called CATREE2, differs from other approaches by simultaneously synthesizing the normal and test mode design behavior. It is particularly suited for top-down system design where a VLSI component's behavior and test method have been fully specified. Preliminary results show that better design solutions are obtained by considering test incorporation during design synthesis than other methods which incorporate test after a structural design solution is formed.>

In this paper the user interface and program organization of the SYMPLE VLSI symbolic layout editor is examined. The user interface is driven by a small interpreter that is constructed from a LISP-like language at run time and has access to a consistent library of menus and graphical information-gathering functions. To improve maintainability, the editor has been constructed in a modular form with well-defined interfaces.

VLSI design requires design methodologies which are tailored to the implementation technology. Symbolic layout has been addressed in the past for MOS technology, while bipolar technology has largely been ignored. This paper describes a novel symbolic design technique which addresses both bipolar and MOS technologies. The technique allows the designer to symbolically layout nMOS, CMOS, and bipolar circuit structures. The symbol set is used for both MOS and bipolar devices in an integrated and consistent way. It is closely related to the mask layout information rather than circuit schematics. Thus, it allows the creation of any circuit structure based on bipolar, MOS, CMOS, BIMOS, and BICMOS technologies. Design examples are given.

Recent advances in integrated circuit technology have involved process development, device, and circuit optimization under scaled design rules. It is advantageous to be able to simulate the overall circuit performance under different conditions. A simulator which performs this task at the logic gate level becomes important. This paper describes such a simulator for digital bipolar integrated circuit families: WATPAC. WATPAC uses the process simulator SUPREM, the device simulator BIPOLE, and the circuit simulator WATAND. The input parameters to WATPAC are entered interactively. These consist of fabrication process parameters, layout design rules, a specification of the logic family, and a WATPAC predefined logic function. The WATPAC output consists of overall circuit performance data for the simulated function block. The output of WATPAC also includes the intermediate outputs of the process simulator, device simulator, and the circuit simulator.

The emitter function iogic (EFL) structure is a bipolar integratable circuit suitable for large-scale-integration (LSI). The structure is a development of current-mode logic and it permits the LSI realization of complex logic functions with similar silicon area and power dissipation to a single conventional ECL gate. In order to use the structure in logic design, some of its properties are developed and a logic design technique is given with examples.

Logic-in-memory (LIM) organization allows central processor functions of computing systems to be combined with memory in regular arrays. The cells of these arrays can themselves be constructed regularly and economically using similar two-level emitter-function logic (EFL) structures. The structure is a development of current-mode logic and it permits the large-scale integration (LSI) realization of three levels of logic with similar silicon area and power dissipation to a single conventional emitter-coupled logic (ECL) gate. It also permits the realization of a D latch in a single structure. The capability of the structure is demonstrated in examples of LIM data transfer and sorting arrays.