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Wen-Wen Hsieh

dblp:59/3468 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 84% Integrated circuit design · 12% Interconnection networks and networks-on-chip · 4%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › delay fault testing
at-speed testing
0.112010
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
hardware verification and test
0.112010
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › power integrity
IR drop optimization
0.112010
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › hardware verification and test › test data compression
x-filling
0.112010
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Integrated circuit design › low-power circuit design
bus encoding
0.112007
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › signal integrity
crosstalk mitigation
0.112007
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Interconnection networks and networks-on-chip
on-chip interconnect
0.012007
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007

Methods — techniques the papers use, named apart from their topics

spatial information · 0.1backward propagation · 0.1prefetch · 0.1deassembler/assembler · 0.1
YearPublicationVenuePosition
2010 A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test
abstract
The IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take theX-fillingapproach to reduce the IR-drop effect during an at-speed test. The main difference between our approach and the previous X-filling approaches lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling is performed. We propose a backward-propagation technique instead of a forward-propagation approach taken in previous work. The experimental results show that our approach can reduce 21.1% of the maximum IR-drop in the best case and 9.1% on the average as compared to previous work.
Wen-Wen Hsieh, Shih-Liang Chen, I-Sheng Lin, TingTing Hwang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2009 Thermal-aware post compilation for VLIW architectures
abstract
Development of a thermal management method to reduce hotspots and to balance the temperature distribution has become an important issue. In this paper, we propose a static thermal management technique at compiler level. The target machine is a VLIW architecture where the compiler is required to schedule instructions to achieve instruction level parallelism (ILP). Two technique are proposed. The first one is register binding to balance the temperature of the register file by taking both spatial and temporal thermal information into consideration. The second one is forwarding methods including forwarding-aware architecture and instruction scheduling to reduce the access count of register file. The experimental results show that by combining the two techniques, the peak temperature reduction can reach 7.89 (°C) in the best case and 7.22 (°C) in average with only 0.9% performance penalty in average.
Wen-Wen Hsieh, TingTing Hwang
ASP-DAC1
2009 A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
abstract
IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take the X-filling approach to reduce IR-drop effect during at-speed test. The main difference between our approach and the previous X-filling methods [7]–[9] lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling is performed. We propose a backward-propagation approach instead of a forward-propagation approach taken in previous work. The experimental results show that we have 42.81% reduction for the worst IR-drop and 45.71% reduction in the average IR-drop as compared to random fill method.
Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang
DATE1
2007 A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design
abstract
A crosstalk effect leads to increases in delay and power consumption and, in the worst-case scenario, to inaccurate results. With the scale down of technology to deep-submicrometer level, the crosstalk effect between adjacent wires becomes more and more serious, particularly between long on-chip buses. In this paper, we propose a deassembler/assembler technique to eliminate undesirable crosstalk effects on bus transmission. By taking advantage of the prefetch process, where the instruction/data fetch rate is always higher than the instruction/data commit rate, the proposed method incurs almost no penalty in terms of dynamic instruction count. In addition, when the bus width is 128 b, the required number of extra bus wires is only 7 as compared to the 85 extra bus wires needed in the work of Victor and Keutzer.
Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1