We propose a powerful hardware architecture for pixel shading, which enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives. The main goal is efficient pixel shading for moderately to finely tessellated geometry, which is not handled well by current GPUs. Our method effectively decouples the cost of pixel shading from the geometric complexity. It thereby enables a wider use of tessellation and fine geometry, even at very limited power budgets. The core idea is to shade over small local grids in parametric patch space, and reuse shading for nearby samples. We also support the decomposition of shaders into multiple parts, which are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.

In this paper a concept for Virtual Machine Vision is proposed using a commercial Computer Aided Robotics software called RobCad. The system utilizes ideal virtual cameras and lights for the simulation of a real vision system. Sensory data is sent to a vision software for data analysis. The Virtual Machine Vision together with the simulation model can be used to offline programming of a vision system. Experiments have been performed by capturing images of a test piece both in the virtual environment and in a physical experimental rig. To evaluate the concept, image analysis has been performed on these images using the same vision software. The results from the vision analysis of both the virtual and the real images are compared and show good agreement. The proposed system seems to be very promising and further development is ongoing.

Parallel programs that modify shared data in a cache-coherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisitions at writes to shared data. This can have a significant impact on performance in a cache-coherent non-uniform memory architecture (NUMA) multiprocessor. By combining a read-request and an ownership acquisition, the write latency and network traffic can potentially be reduced. In this paper we propose a new hardware-based approach far performing this optimization by targeting load-store sequences, which we show is a super-set of migrator sharing. A load-store sequence consists of a global read request followed by a global write action to the same memory, location from the same processor without any intervening access to the same block from any other processor. We use detailed simulation with four benchmark programs including one on-line transaction processing (OLTP) workload and operating system execution to examine the effectiveness of the proposed technique. The results show that the technique is able to reduce write-related latency and network traffic more than previous hardware-based techniques, up to twice as much.

On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the database server and the operating system. One contributing source is a large amount of load-store sequences in the program, resulting in many read misses as well as much global invalidation traffic. In this paper, we characterize the nature of these load-store sequences, and analyze contributing code- and data structures in the database handler, operating system, and system libraries. We explore two conceptually different approaches for detecting load-store sequences; data-centric and instruction-centric, and the goal is to load the cache block exclusively already at the load instruction so that the store instruction can perform locally. Our results were obtained using program-driven simulation of a TPC-B based workload on a four-node multiprocessor. The results show that there is a substantial amount of load-store sequences in the database handler, the operating system, and in system libraries, and about 40% of all global writes belong to such sequences. Even though the techniques were able to reduce the execution time for the application by up to 10%, the complex behavior of the database workload reduced the effectiveness of traditional optimization techniques for migratory sharing.