Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Michael A. Driscoll

dblp:60/614 · DBLP profile ↗
← Back
5ranked-venue papers
2as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 72% Processor architecture and microarchitecture · 28%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis › variable ordering
BDD variable ordering
0.012002
BDD minimization by scatter search · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation › logic synthesis › decision diagrams
binary decision diagram minimization
0.012002
BDD minimization by scatter search · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation › logic synthesis
boolean function representation
0.012002
BDD minimization by scatter search · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation
logic synthesis
0.012002
BDD minimization by scatter search · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation › logic synthesis
variable ordering
0.012002
BDD minimization by scatter search · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Processor architecture and microarchitecture
multithreading
0.011998
A Dynamic Multithreading Processor · MICRO 1998
Processor architecture and microarchitecture
speculative execution
0.011998
A Dynamic Multithreading Processor · MICRO 1998
Processor architecture and microarchitecture
value prediction
0.011998
A Dynamic Multithreading Processor · MICRO 1998
Processor architecture and microarchitecture › multithreading
simultaneous multithreading
0.011998
A Dynamic Multithreading Processor · MICRO 1998

Methods — techniques the papers use, named apart from their topics

simulated annealing · 0.0scatter search · 0.0genetic algorithm · 0.0selective recovery · 0.0data prediction · 0.0
YearPublicationVenuePosition
2002 BDD minimization by scatter search
abstract
Reduced-ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, the authors study the BDD minimization problem based on scatter search optimization. Scatter search offers a reasonable compromise between quality (BDD reduction) and time. On smaller benchmarks it delivers almost optimal BDD size with less time than the exact algorithm. For larger benchmarks it delivers smaller BDD sizes than genetic algorithm or simulated annealing at the expense of longer runtime.
William N. N. Hung, El Mostapha Aboulhamid, Michael A. Driscoll
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
1998 A Dynamic Multithreading Processor
abstract
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and executed speculatively on a simultaneous multithreading pipeline. Data prediction is used to alleviate dependency constraints and enable lookahead execution of the threads. A two-level hierarchy significantly enlarges the instruction window. Efficient selective recovery from the second level instruction window takes place after a mispredicted input to a thread is corrected. The second level is slower to access but has the advantage of large storage capacity. We show several advantages of this architecture: (1) it minimizes the impact of ICache misses and branch mispredictions by fetching and dispatching instructions out-of-order, (2) it uses a novel value prediction and recovery mechanism to reduce artificial data dependencies created by the use of a stack to manage run-time storage, and (3) it improves the execution throughput of a superscalar by 15% without increasing the execution resources or cache bandwidth, and by 30% with one additional ICache fetch port. The speedup was measured on the integer SPEC95 benchmarks, without any compiler support, using a detailed performance simulator.
Haitham Akkary, Michael A. Driscoll
MICRO2
1995 Hardware for Fast Global Operations on Workstation Cluster Multicomputers
abstract
The results presented show that the addition of a secondary network with a wide-tree topology and one or more coordination processors (COPs) to a workstation cluster multicomputer can speed up synchronization, broadcasting, reduction, and several other important global operations by two or three orders of magnitude. The wide tree topology contributes to this by allowing a large number of nodes to simultaneously send commands to a COP and allowing a COP to broadcast a computed value to a large number of nodes simultaneously. Hardware based protection mechanisms in the COP system permit direct user access to the COP network and thus eliminate the overhead of software protocol layers for these global operations. Although the COP system provides a large performance gain for global operations, it increases overall system cost by only 2-3%.
Douglas V. Hall, Michael A. Driscoll
ICDCS2
1995 Accurate Predictions of Parallel Program Execution Time
Michael A. Driscoll, W. Robert Daasch
J. Parallel Distributed Comput.1
1991 Sensitivity Analysis and Mapping Programs to Parallel Architectures
Michael A. Driscoll, Jingsong Fu, Satish Maruti Pai, Chintamani Patwardhan, Liono Sedowijoso, De-Zheng Tang, Kiswanto Thayib
ICPP (2)1